集成電路工藝和版圖設(shè)計(jì)參考-資料下載頁(yè)
2025-01-07 01:54本頁(yè)面
【正文】 ) saveParameter(pgateWidth W) saveParameter(pgateLength L) ngateWidth=measureParameter(length (ngate coincident poly) ) ngateLength=measureParameter(length (ngate inside poly) ) saveParameter(ngateWidth W) saveParameter(ngateLength L) 2022/2/4 Jian Fang 71 LVS 10 10 10 10 10 10 40 EXT LVS Layout versus schematic transistors: parallel or serial Compares electrical circuits: (schematic and extracted layout) 2022/2/4 Jian Fang 72 ERC Electrical rule check Checks electrical circuit: unconnected inputs shorted outputs correct power and ground connection 2022/2/4 Jian Fang 73 Digital design ? Behavioral simulation ? ……………….. ? Simulation/timing verification with estimated backannotation ? Place and route (place and route rules) ? Design Rule Check, DRC (DRC rules) ? Loading extraction (rules and parameters) ? Simulation/timing verification with real backannotation ? Design export ? ……………………….. 2022/2/4 Jian Fang 74 Place and Route ? Generates final chip from gate level list ? Goals: Minimum chip size Maximum chip speed. ? Placement: ? Placing all gates to minimize distance between connected gates ? Floor planning tool using design hierarchy ? Specialized algorithms ( min cut, simulated annealing, etc.) ? Timing driven ? Manual intervention ? Very pute intensive Hierarchy based floor planning Simulated annealing High temperature: move gates randomly Low temperature: Move gates locally Min cut Keep cutting design into equal sized pieces For each cut: Move gates around until minimum connection across cut 2022/2/4 Jian Fang 75 ? Routing: ? Channel based: Routing only in channels between gates (few metal layers: 2) ? Channel less: Routing over gates (many metal layers: 3 6) ? Often split in two steps: ? Global route: Find a coarse route depending on local routing density ? Detailed route: Generate routing layout Channel based Channel less 2022/2/4 Jian Fang 76 ? Performance of submicron CMOS IC’s are to a large extent determined by place amp。 route. ? Loading delays bigger than intrinsic gate delays ? Wire RC delays bees important in submicron ? Clock distribution over plete chip gets critical at operating frequencies above 100Mhz. Number of wires Wire length Local connections Global connections Delay Technology 25ps 50ps 100ps 200ps Gate delay Wire load delay 2022/2/4 Jian Fang 77 2022/2/4 Jian Fang 78 2022/2/4 Jian Fang 79 2022/2/4 Jian Fang 80 集成電路設(shè)計(jì) （物理層） 2022/2/4 Jian Fang 81 2022/2/4 Jian Fang 82 2022/2/4 Jian Fang 83 2022/2/4 Jian Fang 84 2022/2/4 Jian Fang 85 2022/2/4 Jian Fang 86 2022/2/4 Jian Fang 87 2022/2/4 Jian Fang 88 參考文獻(xiàn) : 清華大學(xué)出版社 朱正涌 半導(dǎo)體集成電路 清華大學(xué)出版社 楊之廉 超大規(guī)模集成電路設(shè)計(jì)方法學(xué)導(dǎo)論 ……… 2022/2/4 Jian Fang 89 OVER
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