【正文】 should connect to substrate potential rather than to a power increased surface doping of the lowvoltage Pwell reduces the width of the NSD/Pwell depletion region and causes the electric field across it to electricfield intensities can trigger avalanche multiplication within the depletion resulting debiasing actually improves the collection efficiency of the guard ring, but it may cause problems elsewhere on the die.Figure shows a holecollecting guard ring implemented in a CMOS guard ring consists of a ring of PMoat placed in the Nwell around the source of injected type of guard ring is not very effective because most of the holes flow down to the substrate rather than laterally to the guard ring. Increasing the width of the guard ring does little to improve its effectiveness.The minority carrier guard rings that can be constructed in a CMOS process usually have very limited effectiveness. The two types of guard rings tend to reinforce one another, so the best design practice consists of using both electron and hole collecting guard rings around every device that might inject minority CMOS devices do not inject any substantial level of minority carriers during normal operation, this requirement is satisfied if every device connecting to an output pin receives a guard ring. The designer should examine each pin that neither connects to a power supply nor to substrate potential. Each source/drain region connecting to such a pin requires a guard ring. PMOS transistors require holecollecting guard rings even when placed in their own wells. NMOS transistors require electroncollecting guard rings. A bination of guard rings and backgate contacts should suppress most forms of latchup, but they may prove inadequate for handling the severe minority carrier injection problems associated with inductive kickback and resonance.Analog BiCMOS processes normally include NBLand deepN+.The presence of these layers allows the construction of deep electroncollecting guard rings similar to the one in Figure guard rings are especially effective on designs using a P+ substrate because the builtin potential of the Pepi/substrate interface helps confine the electrons within the deepN+ guard ring on a thinepi P+ process may collect 90%ormore of the electrons injected into the epi.Although analog BiCMOS supports the construction of holeblocking and holecollecting guard rings, these may not be as effective as their standard bipolar counterparts. Analog BiCMOS processes often use a lower NBL doping concentration to minimize lateral lower doping decreases the builtin potential at the NBL/Nwell interface and allows more carriers to enter the lighter NBL also decreases the Gummel number of the parasitic substrate PNP, so a substantial fraction of the carriers may actually perate through the NBL/Nwell interface to the substrate problem bees even more acute on lowvoltage processes using heavily doped wells,since the increased well doping further degrades the builtin potential at the NBL/Nwell interface.The efficiency of hole guard rings suffers if the NBL cannot efficiently block hole flow to the substrate. The addition of a hole blocking guard ring may actually increase substrate injection through a leakyNBL. This seemingly paradoxical behavior probably results from a reduction in the effective volume of the Nwell. The holeblocking guard ring repels holes from the portion of the well it occupies, concentrating them within the remaining volume of the higher concentration of holes near the NBL/Nwell interface increases the injection rate of carriers into the reduction in volume effect should not affect holecollecting guard rings, but the presence of a leaky NBL still reduces their collection efficiency. Analog BiCMOS designs also exhibit excessive substrate resistance. Even if the design uses a P+ substrate, the presence of a lightly doped Pepi makes it difficult to establish a lowresistance substrate contact. Even relatively low levels of substrate injection can produce substantial substrate debiasing. Substrate debiasing can be prevented by blocking minority carriers before they can reach the substrate through the use of hole guard rings. All highcurrent saturating NPN transistors should incorporate such guard rings to prevent substrate debiasing and noise coupling.Analog BiCMOS designs sometimes use a Psubstrate to avoid the necessity of growing two epitaxial layers. Designs constructed on a P substrate are even more susceptible to latchup because electron guard rings no longer benefit from the presence of an electron barrier at the P/P+ designs can still achieve satisfactory levels of immunity to transientinduced latchup providing that every potential source of minority carrier injection is surrounded by a suitable guard the most conservatively designed guard rings may prove unable to handle the severe minority carrier injection problems associated with inductive kickback and resonance. Such designs may require the use of a P+ substrate despite the additional cost associated with the second epitaxial deposition.附錄B 中文譯文CMOS 和 BiCMOS 設(shè)計中的保護(hù)環(huán)CMOS 設(shè)計比標(biāo)準(zhǔn)雙極型更容易引起閂鎖。這個弱點部分來源于現(xiàn)代 CMOS 和BiCMOS 越來越小的尺寸，部分來源于隔離系統(tǒng)的差別。CMOS 工藝通常用摻雜的外延層來代替雙極型工藝中的垂直 P+隔離。輕摻雜會提高由跨過隔離層形成的橫向雙極型晶體管的增益，使少數(shù)載流子注入更容易觸發(fā)硅可控整流器。P 型外延層輕摻雜使它更難提取襯底電流。這種工藝多數(shù)依賴 P+襯底來減少通過襯底的閂鎖的弱點，但是需要對采用保護(hù)環(huán)來防止橫向傳導(dǎo)更加當(dāng)心。圖 N 阱 CMOS 的少子保護(hù)環(huán)（A）收集電子保護(hù)環(huán)（B）收集空穴保護(hù)環(huán)圖 A 是一種 CMOS 工藝中的電子收集保護(hù)環(huán)。這種結(jié)構(gòu)由放進(jìn)一個圍繞注入電子源而布置的 P 外延區(qū)之內(nèi)的 N 型邊溝構(gòu)成。N 型源漏極注入相對較淺，所以它只能載取少部分載流子。這類保護(hù)環(huán)依賴在阱下的 P+襯底來防止少數(shù)載流子繞過保護(hù)環(huán)洞穿到襯底。不幸的是， P+/P一界面產(chǎn)生的電場排斥自襯底多來的電子,并把它們橫向地溝通到鄰近的阱。這一現(xiàn)象使得構(gòu)造阻止少數(shù)載流子向襯底注入的有效勢壘變得很難。把 N 邊溝環(huán)連接到電源而不是連接到地僅僅在邊上有幫助，因為耗盡區(qū)附加的深度只進(jìn)入外延層一點點。N 邊溝放在 P 阱內(nèi)的低壓 CMOS 工藝中，保護(hù)環(huán)應(yīng)該連接到襯底的電位而不是電源。低電壓的 P 阱增加的表面的摻雜減小 N 型源漏極/P 阱耗盡區(qū)的寬度,引起跨過它的電場增強(qiáng)。高場強(qiáng)會在耗盡區(qū)中觸發(fā)雪崩。形成的失偏增加了保護(hù)環(huán)的收集效率，但是會引起芯片其他地方的問題。圖 是 CMOS 工藝中的空穴收集保護(hù)環(huán)。這種保護(hù)環(huán)由在注入空穴源周圍