【正文】 VHDL is one of the strongest tools in hardware description and it is a flexible among the design method. The method given in this paper can reduce the difficulty of digital system design and improve the work efficiency. The use of EDA design technology, hardwaredescription language VHDL description logic means for the system design documents, in MaxplusII tools environment, a topdown design, by the various modules together build a CPLDbased digital clock. The main system chips used EPM7128SLC84, make up of the clock module, control module, time module, data decoding module, display and broadcast module. After piling the design and simulation procedures, the programmable logic device to download verification, the system can plete the hours, minutes and seconds respectively, using keys to modify, cleared , start and stop the digital clock. Key words: Hardware description language,VHDL, Digital circuit design, digital clock 黃河科技學(xué)院畢業(yè)設(shè)計(jì)說明書 第 III 頁 目 錄 1 緒論 ....................................................................................................................................... 1 課題背景 ......................................................................................................................... 1 本課題研究的內(nèi)容 ......................................................................................................... 1 2 總體設(shè)計(jì)方案 ....................................................................................................................... 3 3 單元模塊電路設(shè)計(jì) ............................................................................................................... 4 時(shí)間顯示電路模塊設(shè)計(jì) ................................................................................................. 4 按鍵及指示燈電路模塊的設(shè)計(jì) ..................................................................................... 5 蜂鳴器及有源晶振電路的設(shè)計(jì) ..................................................................................... 7 CPLD 編 程下載電路的設(shè)計(jì) .......................................................................................... 8 電源電路的設(shè)計(jì) ............................................................................................................. 9 變壓器次 級(jí) 電壓估算 .............................................................................................. 9 變壓器輸入功率的計(jì)算 .......................................................................................... 9 濾 波電容參數(shù)的選取 ............................................................................................ 10 EPM7128SLC84 器件介紹 ........................................................................................... 10 4 CPLD 編程設(shè)計(jì) .................................................................................................................. 11 系統(tǒng)信號(hào)的定義及頂層模塊 ........................................................................................ 11 時(shí)鐘節(jié)拍產(chǎn)生模塊 ....................................................................................................... 12 模式選擇功能模塊 ........................................................................................................ 14 快速時(shí)間設(shè)置功能模塊 ............................................................................................... 16 秒、分、時(shí)計(jì)時(shí)與時(shí)間調(diào)整模塊 ............................................................................... 16 鬧鈴時(shí)間設(shè)置模塊 ........................................................................................................ 18 鬧鈴與整點(diǎn)報(bào)時(shí)模塊 .................................................................................................... 19 七段顯示譯碼模塊 ....................................................................................................... 20 LED 顯示模塊 ............................................................................................................... 22 5 系統(tǒng)功能仿真 ..................................................................................................................... 25 黃河科技學(xué)院畢業(yè)設(shè)計(jì)說明書 第 IV 頁 時(shí)鐘節(jié)拍產(chǎn)生模塊的仿真波形 ................................................................................... 25 模式選擇功能模塊的仿真波形 ................................................................................... 26 鬧鈴設(shè)置功能模塊的仿真波形 ................................................................................... 27 七段譯碼功能模塊的仿真波形 ................................................................................... 28 LED 顯示功能模塊的仿真波形 ................................................................................... 30 系統(tǒng)總體功能仿真波形 ............................................................................................... 31 總 結(jié) ..................................................................................................................................... 32 致 謝 ..................................................................................................................................... 33 參考文獻(xiàn) ................................................................................................................................. 34 附錄 A：基于 CPLD 的多功能數(shù)字鐘電路圖 ..................................................................... 35 附錄 B：基于 VHDL語言的時(shí)、分、秒等電路的源碼 .................................................... 36 黃河科技學(xué)院畢業(yè)設(shè)計(jì)說明書 第 1 頁 1 緒論 課題背景 我們已經(jīng)進(jìn)入了數(shù)字化和信息化的時(shí)代，其特點(diǎn)是各種數(shù)字產(chǎn)品的廣泛應(yīng)用。生產(chǎn)制造技術(shù)以微細(xì)加工技術(shù)為代表，目前已進(jìn)展到深亞微米階段，可以在幾平方厘米的芯片上集成數(shù)千萬個(gè)晶體管 [1]。這樣不僅可以通過芯片設(shè)計(jì)實(shí)現(xiàn)各種邏輯功能，而且由于管腳定義的靈活性，減輕了原理圖和印制 板設(shè)計(jì)的工