基于fpga的等精度數(shù)字頻率計(jì)的設(shè)計(jì)相關(guān)中英對(duì)照外文文獻(xiàn)翻譯高質(zhì)量人工翻譯原文帶出處(5)-資料下載頁(yè)
2024-12-03 16:39本頁(yè)面
【導(dǎo)讀】數(shù)字頻率計(jì)是通信設(shè)備、音、視頻等科研生產(chǎn)領(lǐng)域不可缺少的測(cè)量?jī)x器。分和數(shù)碼顯示部分外，其余全部在一片F(xiàn)PGA芯片上實(shí)現(xiàn)。整個(gè)系統(tǒng)非常精簡(jiǎn)，且具有靈活的現(xiàn)場(chǎng)可更改性。直接測(cè)量法,即在一定的閘門時(shí)間內(nèi)測(cè)量被測(cè)信號(hào)的脈沖個(gè)數(shù)。間接測(cè)量法,例如周期測(cè)頻法、VF轉(zhuǎn)換法等。間接測(cè)頻法僅適用測(cè)量?；趥鹘y(tǒng)測(cè)頻原理的頻率計(jì)的測(cè)量精度將隨被測(cè)信號(hào)頻率的下降而降低,個(gè)頻率區(qū)域能保持恒定的測(cè)試精度。頻率測(cè)量方法的主要測(cè)量預(yù)置門控信號(hào)。能力限制,實(shí)際的時(shí)間寬度較少,一般可在10～011s間選擇,即在高頻段時(shí),范圍等精度測(cè)量,減少了低頻測(cè)量的誤差。每個(gè)計(jì)數(shù)器中的CEN輸入端為使能端，用來(lái)控制計(jì)數(shù)。平常計(jì)數(shù)式的8位頻率計(jì)只有幾百元就。有些頻率計(jì)帶有溢出功能，即把最高。位溢出不顯示而只顯示后面的位，以便達(dá)到提高位數(shù)的目的。假設(shè)你用1ns的頻率計(jì)要分辨出1e-12. 而假設(shè)你有另外一個(gè)頻率計(jì)的分辨是。的延遲時(shí)間較短，門電路的延遲時(shí)間相對(duì)較長(zhǎng)。
【正文】 units, it saves CPLD internal resources. Synchronization and multicycle latency to quantify the method of bining The formula is: T=n0t0+n1t1n2t1 On, n0 for the filling pulse of value。 t0 for filling pulse cycle, that is 100 ns。 n1 for a short period of time at Δ t1 corresponding delay the number of modules。 n2 for a short period of time at Δ t2 corresponding delay unit Number。 t1 quantify delay devices for the delay delay unit volume ( ns). In this way, using multicycle synchronization and realized the gate and measured signal synchronization。 Delay of using quantitative measurement of the original measured not by the two short intervals, to accurately measure the size of the actual gate, it raised frequency measurement accuracy. The frequency synthesizer output frequency signal can only be transferred to the minimum 10 Hz, XDU17 as a standard of measurement can be calculated prototype frequency measurement accuracy. For example, the measured signal is measured at MHz MHz signal to , from the calculation can be seen above, the resolution of the prototype has reached ns order of magnitude below from the perspective of theoretical analysis to illustrate this point. It has been anal yzed,multicycle synchronization frequency measurement, the measurement uncertainty: When the input f0 10 MHz, 1 s gate time, the uncertainty of measurement of 177。1107/s. When the measurement and quantification of delay circuit with short intervals bined, the uncertainty of measurement can be derived from the following. In the use of cycle synchronization, multianalyte Tx for the cycle value of T0 time base for the introduction of the cycle. Tx= NT0+△ t1△ t2 Delay circuit and quantitative bined: Tx= NT0+(N1N2)td177。δTx Here, δ Tx not for the accuracy of the measurement. On the decline of the share: \δTx≤177。2td From the details of the measuring accuracy of this method depends on the td, and its direct impact on the stability and size of the uncertainty of measurement. Therefore, the application of methods, counters can be achieved within the entire frequency range, such as the accuracy of measurement, and measurement accuracy is significantly improved, measuring improvement in resolution to ns, and the elimination of the word 177。 a theoretical error, the accuracy is increased by 20 times. CONCLUSION This paper presents a new method of measuring frequency. Based on the frequency of this method of digital integrated circuit in a CPLD, greatly reduced the volume of the entire apparatus, improved reliability, and a highresolution measurements. 5. Frequency of VHDL Design ALTERA use of the FPGA chip EPF10K10 panies, the use of VHDL programming language design accuracy of frequency, given the core course, ISPEXPER simulation, design verification is successful, to achieve the desired results. Compared to the traditional frequency, the frequency of FPGA simplify the circuit board design, increased system design and the realization of reliability, frequency measurement range of up to 100 MHz and achieve a digital system hardware and software, which is digital logic design the new trend This design uses the AL TERA EPF10K10 FPGA chip, the chip pin the delay of 5 ns, frequency of 200 MHz, the standardization of application VHDL hardware description language has a very rich data types, the structure of the model is hierarchical, The use of these rich data types and levels of the structure model of a plex digital system logic design and puter simulation, and gradually improve after the automatic generation integrated to meet the requirements of the circuit structure of the digital logic can be realized, then can be downloaded to programmable logic devices, to plete design tasks. from Vin for Programmable Logic page7688
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