基于fpga的等精度數(shù)字頻率計(jì)的設(shè)計(jì)相關(guān)中英對(duì)照外文文獻(xiàn)翻譯高質(zhì)量人工翻譯原文帶出處(5)(編輯修改稿)
2025-01-08 16:39 本頁(yè)面
【文章內(nèi)容簡(jiǎn)介】 e the automatic conversion, and expanded the range of frequency measurement。 realization of the entire scope of measurement accuracy, reduce the lowfrequency measurement error. 2 .Frequency of achieving Frequency Measurement accuracy of such method. Can be simplified as shown in the diagram. Map CNT1 and CNT2 two controllable counter, standard frequency (f) signal from the CN F1 clock input cI K input, the signal measured after the plastic (f) CNT2 clock input cI K input. Each counter in the CEN input as enable end, used to control the counter count. When the gate signal is HIGH Preferences (Preferences start time). Signal measured by the rising edge of the D flipflop input, launched at the same time with two counts of juice。 Similarly, when preferences for low gate signal (the end of Preferences time), the rising edge of the measured signals through D Trigger output end of the counter to stop counting. the median frequency of relevant indicators Median: At the same time the figures show that up to the median. The usual eightcount frequency of only several hundred yuan can buy. For high precision measurements, nine just beginning, the middle is 11, 13 can be relatively high. Overflow of:the ability to promote itself to overflow the equivalent of the total. Some of the frequency with overflow function, which is the highest overflow does not display only shows that the bit behind, in order to achieve the purpose of the median. Here is the estimated value of individual indicators. Speed: namely, the number of per second. With the high number of measurement particularly slow but also lose its significance. Counting of the usual eight frequency measurement 10 MHz signals, one second gate will be 10000000 Hz, which is actually seven (equivalent to the median number of mon admission after the value), to obtain eight needed 10 seconds gate 。 to obtain nine needed 100 seconds gate, followed by analogy, shows that even the permission of 11 need 10,000 second measurement time. But in any case, or seven per second. Therefore, to fast must be a few high speed. Distinction: it is like a minimum voltage meter can tell how much voltage indicators are similar, the smaller the better, unit ps (picoseconds). 1000ps = 1ns. Suppose you use the frequency of 1 ns to differentiate between an e12 error, we need a ns/1e12 = 1000 seconds. Also assume that you have a frequency resolution of 100 ps, the measurement time can be shortened by 10 times for 100 seconds, or can be in the same 1000 second measured under an e14 Error. 4. Time and Frequency Measurement Compared to traditional methods of circuit design, EDA technology uses VHDL language to describe circuit system, including circuit structure, behavior, function and interface logic. Verilog HDL description of a multilevel system hardware functions, and support topdown design features. Designers can not understand the hardware structure. Start from the system design, on the top floor of a system block diagram of the structure and design, in a diagram with Verilog HDL acts on the circuit description and simulation and error correction, and then the system level verification, and finally use logic synthesis optimization tool to create specific gatelevel logic circuit list, download to the specific FPGA device to in order to achieve FPGA design. Time and frequency measurement is an important area of electronic measurement. Frequency and time measurement has been receiving increasing attention, length, voltage, and other parameters can be transformed into a frequency measurement and related technologies to determine. Based on the more traditional method of synchronization cycle, and has proposed a multicycle synchronization and quantitative method of measuring delay frequency method. The most simple method of measuring the frequency of direct frequency measurement method. Direct Frequency Measureme
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