【正文】 idation Etch Remove mask SiNx SiO2 trench SIMIT 23 SMIC 典型 CMOS工藝流程模塊 Well Formation “ Well” is a doped region where MOSFET is formed Electrically isolated NMOS and PMOS transistors in separate wells fabricated on the same substrate in CMOS process Lithography steps define regions where wells are formed SIMIT 24 SMIC 典型 CMOS工藝流程模塊 Well Formation Change mask Nwell chain implantation Pwell chain implantation Mask Remove mask Anneal SIMIT 25 SMIC Ion Implantation Boundary SIMIT 26 SMIC ? Thermal process to rearrange atoms in silicon matrix and to remove defects in the material ? Often used after implantation to place dopant atoms to locations where they can bee “activated” ? In more advanced processes, performed at very rapid heating rates and short times to minimize diffusion transport – “Rapid Thermal Processing” (RTP) or “Rapid Thermal Annealing” (RTA) 熱退火 (Annealing) SIMIT 27 SMIC ? Atomistic view of doping with ion implantation, followed by annealing ? Before doping: atoms in silicon are arranged in an orderly crystalline structure ? After annealing: the crystalline order is restored, but with dopant atoms now occupying some locations formerly occupied by silicon atoms ? During implantation: dopant ions are “shot” into silicon and disrupt silicon crystal’s orderly arrangement Dopant ions 熱退火 (Annealing) SIMIT 28 SMIC 典型 CMOS工藝流程模塊 Gate Formation Typically made out of heavily doped polysilicon SIMIT 29 SMIC 典型 CMOS工藝流程模塊 Gate Formation Strip thin SiO2 layer Grow gate SiO2 layer gate SiO2 layer Polysilicon gate Etch Remove Mask Mask Deposit Polysilicon SIMIT 30 SMIC 典型 CMOS工藝流程模塊 Source/Drain Formation Source/drain formation consists of: ?Source/Drain extension (LDD) implant ?HALO/Pocket implant : to prevent expansion of drain depletion region into lightly doped channel region – “punchthrough suppression” ?Source/Drain implant: high dose implant to reduce the S/D resistance LDD Halo LDD Halo SIMIT 31 SMIC 典型 CMOS工藝流程模塊 Source/Drain Mask implantation Remove mask Source drain extension ?Source/Drain extension (LDD) implant SIMIT 32 SMIC ?HALO/Pocket formation Mask quad implantation Remove mask 典型 CMOS工藝流程模塊 Source/Drain SIMIT 33 SMIC ?Spacer Formation Mask implantation Remove mask 典型 CMOS工藝流程模塊 Source/Drain Create Spacer SIMIT 34 SMIC 35 ? 微電子技術(shù)成就 ? MOSFET器件發(fā)展歷程 ? 典型 CMOS工藝流程模塊 ? 典型 CMOS制作工藝流程 ? MOSFET器件面臨的挑戰(zhàn) ? MOS器件結(jié)構(gòu)研究最新進(jìn)展 ? FinFET器件研究進(jìn)展 ? 可供選擇的新穎器件 典型 CMOS工藝流程 Isolation Psub (Silicon wafer) SiN (Nitride) Pad oxide ?Wafer Start ?PAD Oxidation (stress buffer) ?SiN (Nitride) Deposition ?Lithography : ?. coating ?Stepper Exposure ?Development Photo Resistor coating Diffusion mask Stepper Exposure Diffusion . Psub (Silicon wafer) SiN (Nitride) Pad oxide SIMIT 36 SMIC Diffusion . Psub (Silicon wafer) SiN (Nitride) Pad oxide STI STI 典型 CMOS工藝流程 – Isolation (cont) ?Trench (STI) Plasma Etching ?SiN Etching ?Silicon Etching ?Photo Resistor remove SIMIT 37 SMIC 典型 CMOS工藝流程 – Isolation (Cont) ?HDPCVD STI Refill ?Liner Oxide Growth ?HDPCVD Oxide Deposition ?STI Furnace Densification ?Sti Cmp ?Sin Remove Diffusion . Psub (Silicon wafer) SiN (Nitrid) Pad oxide STI STI SIMIT 38 SMIC NWELL Mask 典型 CMOS工藝流程 Well formation . Coating NWELL . Stepper Exposure ?NWELL Formation : ? NWELL PR Coating ? NWELL Lithography ? Development ? NWELL Implant ? PR Stripping ?PWELL Formation : ? PWELL PR Coating ? PWELL Lithography ? Development ? PWELL Implant ? PR Stripping Psub(Silicon) Sac. oxide STI PWELL NWELL P WELL Mask Stepper Exposure NWELL Implant 1. NWELL 1 2. NWELL 2 7. P MOS VT 8. P MOS antipunch PPPN MOS N MOS SIMIT 39 SMIC 典型 CMOS工藝流程 Gate Oxide and POLY PR coating Psub (Silicon) NWELL PWELL Gate Oxide TG Mask Stepper Exposure Gate Oxide 2 UPOLY growth? Gate Oxide Formation : ? Thick Gate Oxide Growth ? PR Coating ? TG Lithography ? Development ? RCAA Wet Etching ? PR Stripping ? Thin Gate Oxide Growth ? Poly Growth ? Undoped POLY Growth ? N+POLY PR Coating