【導(dǎo)讀】基于VHDL語言的8位RISC-CPU的設(shè)計(jì)。外文翻譯（原文）

　　

【正文】 Figure Block Diagram of MIPS Data Memory Unit Dmemory module (implements the data memory for the MIPS puter) LIBRARY IEEE。 USE 。 USE 。 USE 。 LIBRARY altera_mf。 USE 。 ENTITY dmemory IS PORT( read_data OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 address IN STD_LOGIC_VECTOR( 7 DOWNTO 0 )。 write_data IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 MemRead, Memwrite IN STD_LOGIC。 外文翻譯（原文） 20 clock, reset IN STD_LOGIC )。 END dmemory。 ARCHITECTURE behavior OF dmemory IS SIGNAL write_clock STD_LOGIC。 BEGIN data_memory altsyncram GENERIC MAP ( operation_mode = SINGLE_PORT, width_a = 32, widthad_a = 8, lpm_type = altsyncram, outdata_reg_a = UNREGISTERED, Reads in mif file for initial data memory values init_file = , intended_device_family = Cyclonelpm_widthad = 8) PORT MAP ( wren_a = memwrite, clock0 = write_clock, address_a = address, data_a = write_data, q_a = read_data )。 Load memory address amp。 data register with write clock write_clock = NOT clock。 END behavior。 MIPS data memory is initialized to the value specified in the file shown in Figure . Note that the address displayed in the file is a word address and not a byte address. Two values, 0x55555555 and 0xAAAAAAA, at byte address 0 and 4 are used for memory data in the short test program. The remaining locations are all initialized to zero. Figure MIPS Data Memory Initialization File, 外文翻譯（原文） 21 Simulation of the MIPS Design The toplevel file is piled and used for simulation of the MIPS. It uses VHDL ponent instantiations to connect the five submodules. The values of major busses and important control signals are output at the top level for use in simulations. A reset is required to start the simulation with PC = 0. A clock with a period of approximately 200ns is required for the simulation. Memory is initialized only at the start of the simulation. A reset does not reinitialize memory. The execution of a short test program can be seen in the MIPS simulation output shown in Figure . The program loads two registers from memory with the LW instructions, adds the registers with an ADD, and stores the sum with SW. Next, the program does not take a BEQ conditional branch with a false branch condition. Last, the program loops back to the start of the program at PC = 000 with another BEQ conditional branch with a true branch condition. Figure Simulation of MIPS test program MIPS Hardware Implementation on the FPGA Board A special version of the top level of the MIPS, , is identical to except that it also contains a VGA video output display driver. As seen in Figure , this driver displays the hexadecimal value of major busses in the MIPS processor on a monitor. The video character generation technique used is discussed in Chapter 10. On the FPGA boards, it also displays the PC in the LCD or LED displays. All FPGA boards use pushbuttons for the clock and reset inputs. The 外文翻譯（原文） 22 clock pushbutton toggles the processor clock so you can see the data changes occurring on each clock edge as you step through MIPS machine instructions. This toplevel module should be used instead of after the design has been debugged in simulations. The final design with video output is then downloaded to the FPGA chip on the board. The video driver uses two M4K RAM embedded memory blocks for format and character font data. After simulation with , repile using and download the design to the FPGA board for hardware verification. Attach a VGA monitor to the board‘s VGA connector. Any changes or additions made to top level signal names in and other modules as suggested in the exercises will need to also be cut and pasted into . Figure MIPS with Video Output generated by UP3 Board For Additional Information The MIPS processor design and pipelining are described in the widelyused Patterson and Hennessy textbook, Computer Organization and Design The HardwareSoftware Interface, Third Edition, Man Kaufman Publishers, 2020. The MIPS instructions are described in Chapter 2 and Appendix A of this text. The hardware design of the MIPS, used as the basis for this model, is described in Chapters 5 and 6 of the Patterson and Hennessy text. SPIM, a free MIPS R2020 assembly language assembler and PCbased simulator developed by James Larus, is available free from 外文翻譯（原文） 23 The reference manual for the SPIM simulator contains additional explanations of all of the MIPS instructions. The MIPS instruction set and assembly language programming is also described in J. Waldron, Introduction to RISC Assembly Language Programming, Addison Wesley, 1999, and Kane and Heinrich, MIPS RISC Architecture, Prentice Hall, 1992. Laboratory Exercises 1. Use VHDL to synthesize the MIPS single clock cycle design in the file . After synthesis and simulation perform the following steps: Display and print the timing diagram from the simulation. Verify that the information on the timing diagram shows that the hardware is functioning correctly. Examine the test program in . Look at the program counter, the instruction bus, the register file and ALU outputs, and control signals on the timing diagram and carefully follow the execution of each instruction in the test program. Label the important values for each instruction on the timing diagram and attach a short writeup explaining in detail what the timing diagram shows relative to each instruction39。s execution and correct operation. Return to the simulator and run the simulation again. Examine the ALU output in the timing diagram window. Zoom in on the ALU output during execution of the add instruction and see what happens when it changes values. Explain exactly what is happening at this point. Hint: Real hardware has timing delays. 2. Repile the MIPS model using the file, which generates video output. Dow