【正文】 _1 STD_LOGIC_VECTOR( 4 DOWNTO 0 )。 SIGNAL write_register_address STD_LOGIC_VECTOR( 4 DOWNTO 0 )。 clock,reset IN STD_LOGIC )。 RegWrite IN STD_LOGIC。 read_data_2 OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 USE 。 END IF。 IF reset = 39。 Store PC in register and load next PC on clock edge PROCESS BEGIN WAIT UNTIL ( clock39。139。 send word address to inst. memory address register Mem_Addr = Next_PC。 BEGIN ROM for Instruction Memory data_memory altsyncram GENERIC MAP ( operation_mode = ROM, width_a = 32, widthad_a = 8, lpm_type = altsyncram, outdata_reg_a = UNREGISTERED, Reads in mif file for initial data memory values init_file = , intended_device_family = Cyclone) Fetch next instruction from memory using PC PORT MAP ( 外文翻譯（原文） 13 clock0 = clock, address_a = Mem_Addr, q_a = Instruction)。 SIGNAL clock, reset IN STD_LOGIC)。 SIGNAL Add_result IN STD_LOGIC_VECTOR( 7 DOWNTO 0 )。 LIBRARY altera_mf。 The Instruction Fetch Stage The instruction fetch stage of the MIPS shown in Figure contains the instruction memory, the program counter, and the hardware to increment the program counter to pute the next instruction address. Figure Block Diagram of MIPS Fetch Unit 外文翻譯（原文） 12 Instruction memory is implemented using the Altsyncram megafunction. 256 by 32 bits of instruction memory is available. This requires two of the Cyclone chip‘s M4K RAM memory blocks. Since the Altsyncram memory requires an address register, the PC register is actually implemented inside the memory block. A copy of the PC external to the memory block is also saved for use in simulation displays. Ifetch module (provides the PC and instruction memory for the MIPS puter) LIBRARY IEEE。 Branch = Beq。 MemtoReg = Lw。 WHEN Opcode = 000100 ELSE 39。 WHEN Opcode = 101011 ELSE 39。 WHEN Opcode = 100011 ELSE 39。 WHEN Opcode = 000000 ELSE 39。 END control。 MemWrite OUT STD_LOGIC。 ALUSrc OUT STD_LOGIC。 USE 。 MEM dmemory PORT MAP ( read_data = read_data, address = ALU_Result, write_data = read_data_2, MemRead = MemRead, Memwrite = MemWrite, clock = clock, reset = reset )。 PC_plus_4_out = PC_plus_4, 外文翻譯（原文） 9 Add_result = Add_result, Branch = Branch, Zero = Zero, PC_out = PC, clock = clock, reset = reset )。 Zero_out = Zero。 write_data_out = read_data WHEN MemtoReg = 39。 BEGIN copy important signals to output pins for easy display in Simulator Instruction_out = Instruction。 SIGNAL MemtoReg STD_LOGIC。 SIGNAL RegDst STD_LOGIC。 SIGNAL ALU_result STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 SIGNAL read_data_1 STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 MemRead, Memwrite IN STD_LOGIC。 外文翻譯（原文） 8 END COMPONENT。 ALU_Result OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 Function_opcode IN STD_LOGIC_VECTOR( 5 DOWNTO 0 )。 END COMPONENT。 MemWrite OUT STD_LOGIC。 ALUSrc OUT STD_LOGIC。 clock, reset IN STD_LOGIC )。 ALU_result IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 COMPONENT Idecode PORT( read_data_1 OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 Zero IN STD_LOGIC。 ARCHITECTURE structure OF TOP_SPIM IS COMPONENT Ifetch PORT( Instruction OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 Output important signals to pins for easy display in Simulator PC OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 )。Value of memory at address A = Register 4 The MIPS Iformat instruction, BEQ, branches if two registers have the same value. As an example, the instruction BEQ $1, $2, LABEL jumps to LABEL if register 1 equals register 2. A branch instruction‘s address field contains the offset from the current address. The PC must be added to the address field to pute the branch address. This is called PCrelative addressing. LW and SW instructions contain an offset and a base register that are used for array addressing. As an example, LW $1, 100($2) adds an offset of 100 to the contents of register 2 and uses the sum as the memory address to read data from. The value from memory is then loaded into register 1. Using register 0, which always contains a 0, as the base register disables this addressing feature. Table MIPS Processor Core Instructions 外文翻譯（原文） 3 A summary of the basic MIPS instructions is shown in Table . In depth explanations of all MIPS instructions and assembly language programming examples can be found in the references listed in section . A hardware implementation of the MIPS processor core based on the example in the widely used textbook, Computer Organization and Design The HardwareSoftware Interface by Patterson and Hennessy, is shown in Figure . This implementation of the MIPS performs fetch, decode, and execute in one clock cycle. Starting at the left in Figure , the program counter (PC) is used to fetch the next address in instruction memory. Since memory is byte addressable, four is added to address the next 32bit (or 4byte) word in memory. At the same time as the instruction fetch, the adder above instruction memory is used to add four to the PC to generate the ne xt address. The output of instruction memory is the next 32bit instruction. The instruction‘s opcode is then sent to the control unit and the function code is sent to the ALU control unit. The instruction‘s register address fields are used to address the twoport register file. The twoport register file can perform two independent reads and one write in one clock cycle. This implements the decode 外文翻譯（原文） 4 operation. Figure MIPS Single Clock Cycle Implementation The two outputs of the register file then feed into the data ALU inputs. The control units setup the ALU operation required to execute the instruction. Next, Load and Store instructions read or write to data memory. Rformat instructions bypass data memory using a multiplexer. Last, Rformat and Load instructions write back a new value into the register file. PCrelative branc