【正文】 s execution and correct operation. Return to the simulator and run the simulation again. Examine the ALU output in the timing diagram window. Zoom in on the ALU output during execution of the add instruction and see what happens when it changes values. Explain exactly what is happening at this point. Hint: Real hardware has timing delays. 2. Repile the MIPS model using the file, which generates video output. Downlo。 END behavior。 Load memory address amp。 ARCHITECTURE behavior OF dmemory IS SIGNAL write_clock STD_LOGIC。 外文翻譯（原文） 20 clock, reset IN STD_LOGIC )。 write_data IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 ENTITY dmemory IS PORT( read_data OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 LIBRARY altera_mf。 USE 。 The Data Memory Stage The data memory stage of the MIPS core shown in Figure contains the data memory. To speed synthesis and simulation, data memory is limited to 256 locations of 32bit memory. Data memory is implemented using the Altsyncram megafunction. Memory write cycle timing is critical in any design. The Altsyncram function requires an internal address register with a clock. In this design, the falling clock edge is used to load the data memories internal address register. The rising clock edge starts the next instruction. Two M4K RAM blocks are used for data memory. Two M4K RAM blocks are also used for the 32bit instruction memory. Figure Block Diagram of MIPS Data Memory Unit Dmemory module (implements the data memory for the MIPS puter) LIBRARY IEEE。 END PROCESS。 WHEN OTHERS = ALU_output_mux = X00000000 。 ALU performs ALUresult = A_input B_input WHEN 110 = ALU_output_mux = Ainput Binput。 ALU performs WHEN 100 = ALU_output_mux = X00000000 。 ALU performs ALUresult = A_input + B_input WHEN 010 = ALU_output_mux = Ainput + Binput。 PROCESS ( ALU_ctl, Ainput, Binput ) BEGIN Select ALU operation CASE ALU_ctl IS ALU performs ALUresult = A_input AND B_input WHEN 000 = ALU_output_mux = Ainput AND Binput。 Adder to pute Branch Address Branch_Add = PC_plus_4( 9 DOWNTO 2 ) + Sign_extend( 7 DOWNTO 0 ) 。 B000 amp。039。139。 ALU_ctl( 2 ) = ( Function_opcode( 1 ) AND ALUOp( 1 )) OR ALUOp( 0 )。 Generate ALU control bits ALU_ctl( 0 ) = ( Function_opcode( 0 ) OR Function_opcode( 3 ) ) AND ALUOp(1 )。039。 BEGIN Ainput = Read_data_1。 SIGNAL Branch_Add STD_LOGIC_VECTOR( 8 DOWNTO 0 )。 ARCHITECTURE behavior OF Execute IS 外文翻譯（原文） 18 SIGNAL Ainput, Binput STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 clock, reset IN STD_LOGIC )。 Add_Result OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 )。 Zero OUT STD_LOGIC。 ALUOp IN STD_LOGIC_VECTOR( 1 DOWNTO 0 )。 Sign_extend IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 ENTITY Execute IS PORT( Read_data_1 IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 USE 。 The Execute Stage The execute stage of the MIPS shown in Figure contains the data ALU and 外文翻譯（原文） 17 a branch address adder used for PCrelative branch instructions. Multiplexers that select different data for the ALU input are also in this stage. Figure Block Diagram of MIPS Execute Unit Execute module (implements the data ALU and Branch Address Adder for the MIPS puter) LIBRARY IEEE。 END PROCESS。 AND write_register_address = 0 THEN register_array( CONV_INTEGER( write_register_address)) = write_data。t write to register 0 ELSIF RegWrite = 39。 END LOOP。139。139。 PROCESS BEGIN WAIT UNTIL clock39。 ELSE XFFFF amp。 Instruction_immediate_value WHEN Instruction_immediate_value(15) = 39。 ) ELSE read_data。 Mux to bypass data memory for Rformat instructions write_data = ALU_result( 31 DOWNTO 0 ) WHEN ( MemtoReg = 39。139。 Read Register 2 Operation read_data_2 = register_array( CONV_INTEGER( read_register_2_address) )。 Instruction_immediate_value = Instruction( 15 DOWNTO 0 )。 write_register_address_1 = Instruction( 15 DOWNTO 11 )。 BEGIN read_register_1_address = Instruction( 25 DOWNTO 21 )。 SIGNAL write_register_address_0 STD_LOGIC_VECTOR( 4 DOWNTO 0 )。 外文翻譯（原文） 16 SIGNAL read_register_2_address STD_LOGIC_VECTOR( 4 DOWNTO 0 )。 SIGNAL write_data STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 SIGNAL register_array register_file。 END Idecode。 Sign_extend OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 MemtoReg IN STD_LOGIC。 ALU_result IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 Instruction IN STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 ENTITY Idecode IS PORT( read_data_1 OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 )。 USE 。 The MIPS program is contained in instruction memory. Instruction memory is automatically initialized using the file shown in Figure . This initialization only occurs once during download and not at a reset. For different test programs, the appropriate machine code must be entered in this file in hex. Note that the memory addresses displayed in the file are word addresses while addresses in registers such as the PC are byte addresses. The byte address is four times the word address since a 32bit word contains four bytes. Only word addresses can be used in the *.mif files. 外文翻譯（原文） 14 Figure MIPS Program Memory Initialization File, The Decode Stage The decode stage of the MIPS contains the register file as shown in Figure . The MIPS contains thirtytwo 32bit registers. The register file requires a major portion of the hardware required to implement the MIPS. Registers are initialized to the register number during a reset. This is done to enable the use of shorter test programs that do not have to load all of the registers. A VHDL FOR...LOOP structure is used to generate the initial register values at reset. 外文翻譯（原文） 15 Figure Block Diagram of MIPS Decode Unit Idecode module (implements the register file for the MIPS puter) LIBRARY IEEE。 END PROCESS。 ELSE PC( 9 DOWNTO 2 ) = Next_PC。139。 )。EVENT ) AND ( clock = 39。 ) ) ELSE PC_plus_4( 9 DOWNTO 2 )。 ) A