【正文】 IMES指令周期Swap instructions take 1S + 2N +1I incremental cycles to execute, where S,N and I are defined as sequential (Scycle), nonsequential, and internal (Icycle), respectively.SWAP指令占用1S+2N+1I周期，這里，S、N和I分別定義為順序（S周期）、非順序（N周期）和內(nèi)部（I周期）。ASSEMBLER SYNTAX匯編程序語法SWP{cond}{B} Rd,Rm,[Rn]{cond} Twocharacter condition mnemonic. See Table 32.{B} If B is present then byte transfer, otherwise word transferRd,Rm,Rn Expressions evaluating to valid register numbersExamplesSWP R0,R1,[R2] 。 Load R0 with the word addressed by R2, and。 store R1 at R2.SWPB R2,R3,[R4] 。 Load R2 with the byte addressed by R4, and。 store bits 0 to 7 of R3 at R4.SWPEQ R0,R0,[R1] 。 Conditionally swap the contents of the。 word addressed by R1 with R0.SWP{cond}{B} Rd,Rm,[Rn]{cond} 雙字母條件助記符，見表32{B} 如果出現(xiàn)B為字節(jié)轉(zhuǎn)移，其余為字轉(zhuǎn)移Rd,Rm,Rn 有效寄存器號表示式ExamplesSWP R0,R1,[R2] 。將以R2為地址的字裝入R0，并在R2儲存R1SWPB R2,R3,[R4] 。將以R4為地址的字裝入R2，并在R4儲存R3的0~7位SWPEQ R0,R0,[R1] 。有條件地與R0交換以R1為地址字的內(nèi)容SOFTWARE INTERRUPT (SWI)軟件中斷The instruction is only executed if the condition is true. The various conditions are defined in Table 32. The instruction encoding is shown in Figure 324, below.該指令僅當(dāng)條件為真時執(zhí)行。條件定義見表32。指令編碼見圖324。圖324. 軟件中斷指令The software interrupt instruction is used to enter Supervisor mode in a controlled manner. The instruction causes the software interrupt trap to be taken, which effects the mode change. The PC is then forced to a fixed value (0x08) and the CPSR is saved in SPSR_svc. If the SWI vector address is suitably protected (by external memory management hardware) from modification by the user, a fully protected operating system may be constructed.軟件中斷指令用于進(jìn)入超級用戶模式。該指令產(chǎn)生導(dǎo)致模式改變的軟件中斷陷阱。強(qiáng)制PC為固定值（0x08），CPSR被存入SPSR_svc。如果SWI向量地址從用戶修改方式得到保護(hù)（由外部存儲器管理硬件），就建立起完全受保護(hù)的操作系統(tǒng)。RETURN FROM THE SUPERVISOR從超級用戶模式返回The PC is saved in R14_svc upon entering the software interrupt trap, with the PC adjusted to point to the word after the SWI instruction. MOVS PC,R14_svc will return to the calling program and restore the CPSR.在進(jìn)入軟件中斷陷阱時，PC被存入R14_svc，然后PC指向SWI指令后的字。MOVS PC,R14_svc將返回調(diào)用程序，并再存CPSR。Note that the link mechanism is not reentrant, so if the supervisor code wishes to use software interrupts within itself it must first save a copy of the return address and SPSR.注意鏈接機(jī)制可以再次進(jìn)入，所以如果超級用戶程序希望在自身中使用軟件中斷，必須先復(fù)制返回地址和SPSR。COMMENT FIELD注釋區(qū)The bottom 24 bits of the instruction are ignored by the processor, and may be used to municate information to the supervisor code. For instance, the supervisor may look at this field and use it to index into an array of entry points for routines which perform the various supervisor functions.處理器不理會指令的低24位，或許可用作超級用戶程序的通訊信息。例如，超級用戶可以查看該區(qū)，并用它來標(biāo)記執(zhí)行各種超級用戶功能程序入口點(diǎn)陣列。INSTRUCTION CYCLE TIMES指令周期Software interrupt instructions take 2S + 1N incremental cycles to execute, where S and N are defined as sequential (Scycle) and nonsequential (Ncycle).軟件中斷指令占用2S+1N周期，這里，S和N分別定義為順序（S周期）和非順序（N周期）。ASSEMBLER SYNTAX匯編程序語法SWI{cond} expression{cond} Two character condition mnemonic, Table 32.expression Evaluated and placed in the ment field (which is ignored by ARM920T).ExamplesSWI ReadC 。 Get next character from read stream.SWI WriteI+k” 。 Output a k to the write stream.SWINE 0 。 Conditionally call supervisor with 0 in ment field.SWI{cond} expression{cond} 雙字母條件助記符，見表32expression 估計和放入注釋區(qū)(ARM920T不理睬).ExamplesSWI ReadC 。從讀流程中得到下一個字母SWI WriteI+k” 。在寫流程中輸出‘k’SWINE 0 。有條件調(diào)用注釋區(qū)0超級用戶Supervisor code超級用戶代碼The previous examples assume that suitable supervisor code exists, for instance:0x08 B Supervisor 。 SWI entry pointEntryTable 。 Addresses of supervisor routinesDCD ZeroRtnDCD ReadCRtnDCD WriteIRtn Zero EQU 0ReadC EQU 256WriteI EQU 512Supervisor 。 SWI has routine required in bits 823 and data (if any) in。 bits 07. Assumes R13_svc points to a suitable stackSTMFD R13,{R0R2,R14} 。 Save work registers and return address.LDR R0,[R14,4] 。 Get SWI instruction.BIC R0,R0,0xFF000000 。 Clear top 8 bits.MOV R1,R0,LSR8 。 Get routine offset.ADR R2,EntryTable 。 Get start address of entry table.LDR R15,[R2,R1,LSL2] 。 Branch to appropriate routine.WriteIRtn 。 Enter with character in R0 bits 07. LDMFD R13,{R0R2,R15}^ 。 Restore workspace and return,。 restoring processor mode and flags.COPROCESSOR DATA OPERATIONS (CDP)協(xié)處理器數(shù)據(jù)操作The instruction is only executed if the condition is true. The various conditions are defined in Table 32. The instruction encoding is shown in Figure 325.This class of instruction is used to tell a coprocessor to perform some internal operation. No result is municated back to ARM920T, and it will not wait for the operation to plete. The coprocessor could contain a queue of such instructions awaiting execution, and their execution can overlap other activity, allowing the coprocessor and ARM920T to perform independent tasks in parallel.該指令僅當(dāng)條件為真時執(zhí)行。條件定義見表32。指令編碼見圖325。COPROCESSOR INSTRUCTIONS協(xié)處理器指令The S3C2410X, unlike some other ARMbased processors, does not have an external coprocessor interface. It does not have a onchip coprocessor also.So then all coprocessor instructions will cause the undefined instruction trap to be taken on the S3C2410X. These coprocessor instructions can be emulated by the undefined trap handler. Even though external coprocessor can not be connected to the S3C2410X, the coprocessor instructions are still described here in full for pleteness. (Remember that any external coprocessor described in this section is a software emulation.)圖325. 協(xié)處理器數(shù)據(jù)操作指令Only bit 4 and bits 24 to 31 The coprocessor fields are significant to ARM920T. The remaining bits are used by coprocessors. The above field names a