【正文】 當(dāng)這些“和”接近和超過 Nyquist頻率， Fclk/2，這些“和”就成為樣本之下和反映到重要的邊帶， 0到 Fclk/2。超出輸出范圍時一個 DAC會有一個特有的彎曲特性曲線。 積分線性是一個 DAC的總的線性性 能對一個理想的線性直線的一個衡量。因此，一個有大于 1LSB微分線性的 10比特 DAC可以精確到 9或者更小的比特。當(dāng)輸入碼增加， DAC的輸出必須相應(yīng)增加。 微分線性是指輸出的步進大小為比特到比特。DAC的量化曲線數(shù)字輸入對 應(yīng)模擬輸出的 DAC量化曲線可以看作是理想線性的。一個DAC輸出的模擬電壓取決于輸入的數(shù)字值。 LSB（假設(shè)當(dāng)突刺為 20log(2D)dBc的最壞情況時）。ROM表是通過把所有可能的相位值地址和映射到實際正弦波大小的近似 D比特來產(chǎn)生的。一個相位截短突刺輸出的例子如圖 5所示。相位的跳轉(zhuǎn)由相位截短位累加在基波周圍產(chǎn)生突刺。當(dāng)一個頻率控制字包含一個非零的值在低（ NY1：0）位是裝載到 DDS 系統(tǒng)的，低非零位累加到高 Y 位和使得產(chǎn)生一個相位截短。 如上所示，相位累加器只有高 Y 比特是用來尋址 ROM 表。一個 DDS 系統(tǒng)的假的響應(yīng)是主要由兩個量子化參量確定的。這個在 DAC 輸出的衰減在下面計算出來而且一個 抽樣輸出頻譜。因為時域是卷積的，頻率域就是相當(dāng)于相乘。 DAC 過程的時域結(jié)構(gòu)是 NCO 抽樣輸出值和一個抽樣周期脈沖的卷積。圖 4顯示出時間和頻率域 DAC 過程開始于 NCO 的輸出的表示?；镜暮蛣e的成分發(fā)生在： K*Fclk Fout K*Fclk + Fout 當(dāng) K = ... 1, 0 , 1, 2 ..... 和 K = 0 是 NCO 正弦曲線基本頻率。當(dāng)在時間域里取樣時鐘乘于正弦曲線， 正弦曲線頻率域成分和取樣時鐘需要卷積來產(chǎn)生 NCO 輸出頻率域表示的 NCO 輸出。在時間域里， NCO輸出是一個取樣時鐘邊緣閘門乘于正弦波形式產(chǎn)生的一個推動序列正弦振幅的作用。這個正弦曲線的頻率域表示在指定的頻率里是一個推動的作用。注意到這個表示并非量子化假設(shè)。因此， NCO本質(zhì)上用一個正弦波和用 NCO 的上升 或下降沿輸出參考取樣時鐘對其取樣。 為了理解 DDS 系統(tǒng)中取樣理論的效果，最好看一下時間和頻率域的 DDS 合成過程。 雖然 DDS 系統(tǒng)給設(shè)計者完全地控制復(fù)雜的調(diào)制合成，但是在一個非線性數(shù)字格式的正弦相位和量級的表示卻是復(fù)雜的新設(shè)計。最后，頻率是調(diào)制 是一個基本的 NCO 設(shè)計給出的。假如系統(tǒng)設(shè)計需要幅度調(diào)制如 QAM，可以加入一個量化端口來調(diào)整正弦 ROM 表的輸出。 因為一個 NCO 輸出的一個基于一個數(shù)字表示的相位和正弦波量化形式的載波，所以設(shè)計者可以完全的控制輸出載波的頻率，相位和幅度。由于正弦 ROM 表的大小是跟尋址范圍直接成比例的，因此，不是所有相位累加器的 24 或 32 位都用來作為正弦 ROM表的地址。抽樣相位到正弦量化的轉(zhuǎn)化可以看作是真實的或者虛擬的成分及時地影射。當(dāng)累加器達到N位最大值的時候，累加器翻轉(zhuǎn)然后繼續(xù)。 這個頻率控制字是最后一個抽樣相位值通過一個 N 位加法器的連 續(xù)地累加而成。與歐拉公式（ Euler’ s formula）圖解比較就能最好地理解這兩個表的 NCO 設(shè)計的功能。通過增加 NCO的載波相位調(diào)制的輸出能力可以提高 DDS 系統(tǒng)的設(shè)計。根據(jù) 輸入的參考時鐘抽樣經(jīng)過 NCO 來產(chǎn)生輸出載波。 一個基本的 DDS 系統(tǒng)包括一個數(shù)字振蕩器（ NCO）用來產(chǎn)生輸出載波，和一個數(shù)模轉(zhuǎn)換器（ DAC）用來將從 NCO 過來的數(shù)字式正弦曲線字產(chǎn)生一個抽樣的模擬載波。 本文主旨是給讀者一個基本的 DDS 設(shè)計和寄生輸出響應(yīng)的知識。根據(jù)后面的說明，我們知道 DDS系統(tǒng)還可以使用輸入數(shù)字相位控制字來控制輸出載波的相位。這種形式是頻率控制使得 DDS系統(tǒng)成為需要精確頻率掃描比如雷達尖叫聲或者快速頻率計量器的理想系統(tǒng)。一個適合這個目標(biāo)的數(shù)字式設(shè)計就是直接數(shù)字頻率合成器（ DDS）。 of the symmetrical sine wave form is stored in the ROM. The sine values stored in this table are the 0 to p/2 unsigned values quantized to 8 bits. Thus, the ROM table requires a 6 bit phase address input and outputs a 7 bit amplitude output. The sinlup module processes the phase and amplitude values to produce a plete sine period. Dan Morelli has over 9 years of design and management experience. His areas of expertise include spread spectrum munications (involving GPS, TDRSS, and ), PC chip set and system architecture, cell library development (for ECL devices) and ASIC development. He has been published and has multiple patents awarded and pending. Dan currently works for Accelent Systems Inc., an electronic design consulting pany, where he is a founder and the VP of Engineering. 附錄 4： 中文譯文 數(shù)字頻率合成器 在探討許多復(fù)雜的相位連續(xù)的調(diào)制技術(shù)中，對模擬電路中輸出波形的控制已經(jīng)越來越困難。 of the symmetrical sine wave form and the MSB of the sine wave form is equivalent to the modulated phase module performs the calculations to reconstruct a plete period of the sine wave form from the 188。 189。附錄 3：英文原文 Modulating Direct Digital Synthesizer In the pursuit of more plex phase continuous modulation techniques, the control of the output waveform bees increasingly more difficult with analog circuitry. In these designs, using a nonlinear digital design eliminates the need for circuit board adjustments over yield and temperature. A digital design that meets these goals is a Direct Digital Synthesizer DDS. A DDS system simply takes a constant reference clock input and divides it down a to a specified output frequency digitally quantized or sampled at the reference clock frequency. This form of frequency control makes DDS systems ideal for systems that require precise frequency sweeps such as radar chirps or fast frequency hoppers. With control of the frequency output derived from the digital input word, DDS systems can be used as a PLL allowing precise frequency changes phase continuously. As will be shown, DDS systems can also be designed to control the phase of the output carrier using a digital phase word input. With digital control over the carrier phase, a high spectral density phase modulated carrier can easily be generated. This article is intended to give the reader a basic understanding of a DDS design, and an understanding of the spurious output response. This article will also present a sample design running at 45MHz in a high speed field programmable gate array from QuickLogic. A basic DDS system consists of a numerically controlled oscillator (NCO) used to generate the output carrier wave, and a digital to analog converter (DAC) used to take the digital sinusoidal word from the NCO and generate a sampled analog carrier. Since the DAC output is sampled at the reference clock frequency, a wave form smoothing low pass filter is typically used to eliminate alias ponents. Figure 1 is a basic block diagram of a typical DDS system generation of the output carrier from the reference sample clock input is performed by the NCO. The basic ponents of the NCO are a phase accumulator and a sinusoidal ROM lookup table. An optional phase modulator can also be include in the NCO design. This phase modulator will add phase offset to the output of the phase accumulator just before the ROM lookup table. This will enhance the DDS system design by adding the capabilities to phase modulate the carrier output of the NCO. Figure 2 is a detailed block diagram of a typical NCO design showing the optional phase modulator. FIGURE 1: Typical DDS System. FIGURE 2: Typical NCO Design. To better understand the functions of the NCO design, first consider the basic NCO design which includes only a phase accumulator and a sinusoidal ROM lookup table. The function of these two blocks of the NCO design are best understood when pared to the graphical representation of Euler’s formula ej wt = cos( wt) + jsin( wt). The graphical representation of Euler’s formula, as shown in Figure 3, is a unit vector rotating around the center axis of the real and imaginary plane at a velocity of wrad/s. Plotting the imag