【正文】 ngle bit digital cosine wave output. This cosine wave output es form the MSB and next most significant bit of the phase accumulator. The output frequency of this pin is controlled by the frequency word input. MSIN This output is a single bit digital sine wave output. This sine wave output es from the MSB of the phase modulator. The output frequency of this pin is controlled by the frequency word input and phase offset bythe phase word input. This sine wave output is the same as the SIN output with a phase offset of plus 2p/28 * PHASEWORD. MCOS This output is a single bit digital cosine wave output. This cosine wave output es form the MSB and next most significant bit of the phase modulator. The output frequency of this pin is controlled by the frequency word input and the phase offset by the phase word input. This cosine wave outputis the same as the COS output with a phase offset of plus 2p/28 * PHASEWORD. IDATA This output is a 25 1 pseudo noise random pattern. This output is not a functional part of the NCO design but used to demonstrate phasemodulation using the phase port. QDATA This output is a 25 1 pseudo noise random pattern. This output is not a functional part of the NCO design but used to demonstrate phase modulation using the phase port. Figure 6: The External IO Interface Top Level () The top level of the NCO design instantiates the functional blocks of the NCO design and the PN generator block. PN Generator () This module is not part of the NCO design but is used to produce a sample random data pattern to modulate the carrier output. This module uses the PNCLK input to clock two Gold code 5 bit PN generators. The outputs of the PN generators are IDATA and QDATA outputs. The lower level block of this NCO design consist of a synchronous frequency word input register, a synchronous phase word input register, a 32 bit pipe lined phase accumulator, an 8 bit phase adder, and a sin lockup table. A detailed description of each of the NCO blocks and the PN generator are provided in the following sections. Load Frequency Word () The load frequency word block is a synchronizing loading circuit. The FREQWORD[31:0] input drives a the data input to the 32 bit fwreg register that is sampled on the rising edge of the FWWRN write strobe. The FWWRN strobe also drives the data input to a metastable flip flop fwwrnm that is used in conjunction with a synchronous register fwwrns to produce a FWWRN rising edge strobe. This rising edge strobe loadp1 is then piped for an additional 3 clock cycles producing the load strobes loadp2, loadp3, and loadp4. The load strobes are used to signal when to update the synchronous pipe line 8 bit registers pipefw1, pipefw2, pipefw3, and pipefw4 to the sampled frequency word content. The pipe line registers are concatenated to produce the 32 bit synchronous frequency word output SYNCFREQ[31:0] that is staggered to pensate for the 32 bit pipe lined phase adder. Phase Word Accumulator () The phase accumulator block is a 32 bit accumulator that is pipe lined in 8 bit sections. This module instanciates a schematic captured carry lock ahead CLA adder that has a carry in and carry out port. The synchronous frequency word, staggered to match the pipe lined accumulator, is loaded into the B input of the CLA adders. The sum output of the CLA adders are registered in the pipe registered with the output tied back to the A input of the CLA adders. The carry output of the CLA adders is registered in the pipec registers with the output tied to the next most significant CLA adder carry input. The most significant sum output register pipe4 is assigned to the PHASE output port giving a phase value quantized to 8 bits. A digital sine and cosine value is also calculated from the pipe4 register and brought out of the chip as SIN and COS. Load Phase Word () The load phase word block is a synchronizing loading circuit. The PHASEWORD[7:0] input drives the data input to the 32 bit pwreg register that is sampled on the rising edge of the PWWRN write strobe. The PWWRN strobe also drives the data input to a metastable flip flop pwwrnm that is used in conjunction with a synchronous register pwwrns to produce a FWWRN rising edge strobe. This rising edge strobe load is used to signal when to update the synchronous phase word register phswd. The phswd register is assigned to the synchronous phase word output SYNCPHSWD[7:0]. Phase Modulator () The phase modulator block is used to phase offset the phase accumulator 8 bit quantized output with the synchronous phase word from the load phase word block. This module instantiates a CLA adder with the A input tied to the synchronous phase output and the B input tied to the phase accumulator output. The sum output of the adder is registered in the mphsreg register and assigned to the MODPHASE output port. A modulated version of the sine and cosine values are calculated and brought out of the chip as MSIN and MCOS. Sine Lockup () This module takes the modulated phase value form the phase modulator block and translated the quantized 8 bit value into a sine wave form amplitude value quantized to 8 bits. The translation from phase to amplitude is performed by a sine ROM table that in instantiated in this module. The ROM table is reduced to a 188。根據(jù)數(shù)字輸入控制字以控制輸出頻率， DDS 系統(tǒng)可以用來當作一個允許精確頻率連續(xù)改變相位的鎖相環(huán)（ PLL）。NCO 的基本構成是一個相位累加器和一個正弦 ROM查找表。然后相位累加器的抽樣輸出用來在一個正弦量化值表里進行查找。注意到這個端口沒有在圖 2里表示出來以及這個特色沒有在簡單的快速邏輯 FPGA 設計中論證。圖 4表示在時間和頻率域里 NCO 的處理。 頻率域的結果是在正弦曲線基本頻率的脈沖作用和別的脈沖作用發(fā)生在 K倍的 NCO 時鐘頻率加上或減去基本頻率。這個乘法過程使得 NCO 輸出有一個 sin(x)/x 包絡。相位的截短出現(xiàn)的頻率可以根據(jù)以下計算： Ftrunc = FW(NY1:0)/2NY * Fclk. 一個相位的截短會周期性（以 Ftrunc 速率）相位調制輸出載波提前 2p/28來補償頻率控制字間隔多于 /2Y。 類似于 NCO的 ROM表，一個 DAC也同樣是這樣量子化數(shù)字值為模擬值的。假如 DAC電壓的增加不是對應于一個增加的輸入數(shù)字值，可以說 DAC是缺碼的。這個問題可以通過設置 NCO的輸出到 Fc