【正文】 ry6,carry7:std_logic。signal t1:std_logic。begin U0:t10 port map(clk=clk,clr=clr,carry_out=carry1,ena=t1,cq=y(3 downto 0))。U1:t10 port map(clk=carry1,clr=clr,carry_out=carry2,ena=t1,cq=y(7 downto 4))。U2:t10 port map(clk=carry2,clr=clr,carry_out=carry3,ena=t1,cq=y(11 downto 8))。U3:t6 port map(clk=carry3,clr=clr,carry_out=carry4,ena=t1,cq=y(15 downto 12))。U4:t10 port map(clk=carry4,clr=clr,carry_out=carry5,ena=t1,cq=y(19 downto 16))。U5:t6 port map(clk=carry5,clr=clr,carry_out=carry6,ena=t1,cq=y(23 downto 20))。U6:t10 port map(clk=carry6,clr=clr,carry_out=carry7,ena=t1,cq=y(27 downto 24))。U7:t10 port map(clk=carry7,clr=clr,ena=t1,cq=y(31 downto 28))。u8:fanxiangqi port map(clk=stop,t=t1,clr=clr)。end art。XZSCMK源程序library ieee。use 。use 。entity xzscmk isport(d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(31 downto 0)。 select1,clr:in std_logic。y:out std_logic_vector(31 downto 0))。end entity xzscmk。architecture art of xzscmk isponent select8_1 is port(d0,d1,d2,d3,d4,d5,d6,d7:in std_logic_vector(31 downto 0)。 y:out std_logic_vector(31 downto 0)。 ar:in std_logic_vector(3 downto 0))。 en: in std_logic)。end ponent select8_1。ponent t8 port (clk: in std logic。 clr: in std_logic。 cq: out std_logic_vector(3 downto 0))。end ponent。signal k:std_logic_vector(3 downto 0)。beginu0:select8_1 port map(d0=d0,d1=d1,d2=d2,d3=d3,d4=d4,d5=d5,d6=d6,d7=d7,ar=k(3 downto 0),y=y)。u1:t8 port map(cq=k(3 downto 0),clk=select1,clr=clr)。end art。HXMK源程序library ieee。use 。use 。entity hxmk isport(y0,y1,y2,y3,y4,y5,y6,y7: out std_logic_vector(31 downto 0)。 clk,clr,jishu,stop:in std_logic)。end entity hxmk 。architecture art of hxmk isponent jsmk port(clk,stop,clr:std_logic。 y:out std_logic_vector(31 downto 0))。end ponent。ponent jymk port(d0,d1,d2,d3,d4,d5,d6,d7:in std_logic_vector(31 downto 0)。 clr,jishu:std_logic。 q0,q1,q2,q3,q4,q5,q6,q7:out std_logic_vector(31 downto 0))。end ponent。signal qout:std_logic_vector(31 downto 0)。beginu0:jsmk port map(clk=clk,clr=clr,stop=stop,y=qout)。u1:jymk port map(clr=clr,jishu=jishu,d0=qout,d1=qout,d2=qout,d3=qout,d4=qout,d5=qout,d6=qout,d7=qout,q0=y0,q1=y1,q7=y7,q2=y2,q3=y3,q4=y4,q5=y5,q6=y6)。end art。DCMK源程序library ieee。use 。use 。entity dcmk is port(clk,clr,stop,select1,jishu:in std_logic。 y:out std_logic_vector(31 downto 0))。end entity dcmk。architecture art of dcmk isponent hxmk port(y0,y1,y2,y3,y4,y5,y6,y7: out std_logic_vector(31 downto 0)。 clk,clr,jishu,stop:in std_logic)。end ponent。ponent xzscmkvhd port(d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(31 downto 0)。 select1,clr:in std_logic。y:out std_logic_vector(31 downto 0))。end ponent。signal g1,g2,g3,g8,g4,g5,g6,g7:std_logic_vector(31 downto 0)。beginu0:hxmk port map(y0=g2,y1=g3,y2=g4,y3=g5,y4=g6,y5=g7,y6=g8,y7=g1,clk=clk,clr=clr,stop=stop,jishu=jishu)。u1:xzscmkvhd port map(d0=g1,d1=g2,d2=g3,d3=g4,d4=g5,d5=g6,d6=g7,d7=g8,select1=select1,clr=clr,y=y)。end art。YIMAMK 源程序library ieee。use 。use 。entity yimamk isport(din:std_logic_vector(31 downto 0)。 dout1,dout2,dout3,dout4,dout5,dout6,dout7,dout8: out std_logic_vector(6 downto 0))。end entity yimamk。architecture art of yimamk isponent hc4511 port( din :in std_logic_vector(3 downto 0)。 dout:out std_logic_vector(6 downto 0))。end ponent。begin u0:hc4511 port map(din=din(3 downto 0),dout=dout1)。u1:hc4511 port map(din=din(7 downto 4),dout=dout2)。u2:hc4511 port map(din=din(11 downto 8),dout=dout3)。u3:hc4511 port map(din=din(15 downto 12),dout=dout4)。u4:hc4511 port map(din=din(19 downto 16),dout=dout5)。u5:hc4511 port map(din=din(23 downto 20),dout=dout6)。u6:hc4511 port map(din=din(27 downto 24),dout=dout7)。u7:hc4511 port map(din=din(31 downto 28),dout=dout8)。end art。頂層模塊SHUZIMIAOBIAO的源程序library ieee。use 。use 。entity shuzimiaobiao isport(clk,clr,stop,select1,jishu:in std_logic。 output1,output2 ,output3,output4,output5,output6,output7,output8: out std_logic_vector(6 downto 0))。end entity shuzimiaobiao。architecture art of shuzimiaobiao isponent dcmkport(clk,clr,stop,select1,jishu:in std_logic。 y:out std_logic_vector(31 downto 0))。end ponent。ponent yimamk port(din:std_logic_vector(31 downto 0)。 dout1,dout2,dout3,dout4,dout5,dout6,dout7,dout8: out std_logic_vector(6 downto 0))。end ponent。signal data1 :std_logic_vector(31 downto 0 )。begin u0:dcmk port map(clk=clk,clr=clr,select1=select1,stop=stop,jishu=jishu,y=data1)。u1:yimamk port map(din=data1,dout1=output1,dout2=output2,dout3=output3,dout4=output4,dout5=output5,dout6=output6,dout7=output7,dout8=output8)。end art。39