【正文】 urthermore, the use of nulling resistors to remove the RHP zeros is discussed and optimization criteria are described. A novel technique is presented which allows an amplifier’s frequency and settling performance to be greatly improved without increasing power consumption. Thanks to the small pensation capacitors employed, the approach is amenable for integration and in particular where large load capacitors have to be driven. SPICE simulations based on a m CMOS design are given and found in remarkable agreement with the theoretical analysis. Index Terms—Amplifiers, analog integrated circuits, circuit stability, CMOS analog integrated circuits, CMOSFET power amplifiers, pensation, feedback amplifiers, feedback circuits, frequency pensation, multistage amplifier, zero pensation.I. INTRODUCTIONDue to the decrease in supply voltages, cascode topologies are not suitable for IC applications demanding both high gain and swing, such as highaccuracy and highlinearity circuits, and high (switchedcapacitor) filters. Presently, amplifiers exhibiting dc gains in excess of 100 dB can profitably be implemented with a cascade of three simple stages. Therefore, multistage amplifiers and their frequency pensation have bee increasingly important in modern microelectronics [1]–[4].In the design of twostage amplifiers, it is mon practice to employ the Miller pensation technique since it allows the use of a relatively lowvalued pensation capacitor (which is amplified by the Miller effect) and increases the achievable bandwidth thanks to the wellknown polesplitting feature. It is also known that the stability of Millerpensated amplifiers is deteriorated by a righthalfplane (RHP) zero which must be eliminated in CMOS amplifiers especially in lowpower applications, due to the low transconductance of MOS transistors.Miller pensation can also be applied to multistage amplifiers [5]–[12], and in this context three main possible arrangements have been recognized [4]. The nested Miller (NM) pensation is one of these, and can be profitably used when only the final gain stage is voltageinverting. Several of the NMpensated amplifiers considered in the literature are implemented in bipolar technology or have highdrive capability and are not designed for lowpower CMOS applications [2], [10]. Here, the main effort of researchers has been to improve the by nature poor frequency performance of NMpensated amplifiers. For instance, in [2] a technique which allows the maximization of the gainbandwidth product is described.Although the effects of parasitic zeros introduced by the NM pensation network were not taken into account in the early literature, for lowvoltage lowpower CMOS designs the removal of the righthalfplane (RHP) zero is mandatory and different strategies have been developed. One such design uses a transconductancecapacitance pensation scheme based on the nesting of a basic module (shown in Fig. 1) [4], [19]. The last work describes a systematic (multipath) pensation technique for a generic stage amplifier. However, the approach requires a puteraided procedure to find transconductance values for each amplifier stage (this is a first limitation since transconductances are generally set by other specifications). Moreover, the particular choice of the capacitor values limits the maximum achievable bandwidth and the use of the feedforward transconductance has detrimental effects on the CMRR, as it creates an asymmetrical inputoutput path increasing the monmode gain by approximately one gain stage.Recently, another approach for RHP zero removal was reported [14]. It employs an auxiliary inverting stage which is used to increase (with the Miller effect) the internal pensation capacitor. This auxiliary stage is not loaded by the external load capacitor , but only by parasitic capacitances. In such a manner small pensation capacitors can be used allowing increased bandwidth and slewrate at the expense of a limited increase in circuit plexity and power dissipation. However, the proposed implementation [20, Fig. 6] has the dampingfactorcontrol stage which operates in openloop conditions, thus, its bias point stability is endangered. Except for the approach described in [15], in all existing works, the use of nulling resistors to provide RHP zero cancellation have been a priori excluded. It is our conviction that this method remains one of the best suited because of its inherent circuitlevel simplicity, lowvoltage lowpowerrequirements, and the possibility of converting a RHP zero into a lefthalfplane (LHP) one.The purpose of this paper is twofold.? The NM pensation is reviewed.? An efficient approach based on nulling resistors is presented.Section II presents a new, simple designoriented method which, by neglecting the effects of parasitic zeros, provides results in agreement with those reported in previously published works. As customary in amplifier design, we use the phase margin ( ) as the main design parameter which, in conjunction with the gainbandwidth product (GBW), is the most meaningful and can simply be set by a pencilandpaper putation. Techniques for the removal of RHP zeros using nulling resistors are also dealt with in Section III, and an optimization of the method suggested in [15] is given. In these above two sections an assessment and optimization of previously presented works is hence attempted. Regarding the second point, a pensation approach which exploits double pole–zero cancellation is presented in Section IV. Finally, SPICE simulations on a threestage amplifier example implemented in a m CMOS technology and powered with a 2V supply are provided in Section V.II. NM COMPENSATIONIn this section, the NM pensation technique is reviewed by use of a novel designoriented approach. Let us consider the smallsignal equivalent circuit of a threestage amplifier depicted in Fig. 2 including the pensation capacitors. Param