【正文】 Indexing Pointers Description Pointer Syntax Pointer Modified *R No R can be any register In this case the pointers are used but not modified. Indexing Pointers Description Pointer + Preoffset Preoffset Syntax Pointer Modified *R *+R[disp] *R[disp] No No No ? [disp] specifies the number of elements size in DW (64bit), W (32bit), H (16bit), or B (8bit). ? disp = R or 5bit constant. ? R can be any register. In this case the pointers are modified BEFORE being used and RESTORED to their previous values. Indexing Pointers Description Pointer + Preoffset Preoffset Preincrement Predecrement Syntax Pointer Modified *R *+R[disp] *R[disp] *++R[disp] *R[disp] No No No Yes Yes In this case the pointers are modified BEFORE being used and NOT RESTORED to their Previous Values. Indexing Pointers Description Pointer + Preoffset Preoffset Preincrement Predecrement Postincrement Postdecrement Syntax Pointer Modified *R *+R[disp] *R[disp] *++R[disp] *R[disp] *R++[disp] *R[disp] No No No Yes Yes Yes Yes In this case the pointers are modified AFTER being used and NOT RESTORED to their Previous Values. Description Pointer + Preoffset Preoffset Preincrement Predecrement Postincrement Postdecrement Syntax Pointer Modified *R *+R[disp] *R[disp] *++R[disp] *R[disp] *R++[disp] *R[disp] No No No Yes Yes Yes Yes ? [disp] specifies elements size in DW, W, H, or B. ? disp = R or 5bit constant. ? R can be any register. Indexing Pointers Modify and testing the code This code now performs the following operations: a0*x0 + a1*x1 + a2*x2 + ... + aN*xN MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 loop LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 [B0] B .S loop The Pointer A7 is now initialised. MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 pt3, A7 MVKH .S2 pt3, A7 MVKL .S2 count, B0 loop LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 [B0] B .S loop STH .D A4, *A7 Store the final result What is the initial value of A4? A4 is used as an accumulator, so it needs to be reset to zero. MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 pt3, A7 MVKH .S2 pt3, A7 MVKL .S2 count, B0 ZERO .L A4 loop LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 [B0] B .S loop STH .D A4, *A7 How can we add more processing power to this processor? .S1 .M1 .L1 .D1 A0 A1 A2 A3 A4 Register File A . . . Data Memory A15 32bits Increasing the processing power! (1) Increase the clock frequency. (2) Increase the number of Processing units. .S1 .M1 .L1 .D1 A0 A1 A2 A3 A4 Register File A . . . Data Memory 32bits A15 Increasing the processing power! Two side Processing units(A and B) Data Memory .S1 .M1 .L1 .D1 A0 A1 A2 A3 A4 Register File A . . . A15 32bits .S2 .M2 .L2 .D2 B0 B1 B2 B3 B4 Register File B . . . B15 32bits Can they exchange operands? .S1 .M1 .L1 .D1 A0 A1 A2 A3 A4 Register File A . . . A15 32bits .S2 .M2 .L2 .D2 B0 B1 B2 B3 B4 Register File B . . . B15 32bits Data Memory The answer is YES but there are limitations. ? To exchange operands between the two sides, some cross paths or links are required. What is a cross path? ? A cross path links one side of the CPU to the other. ? There are two types of cross paths: ? Data cross paths. ? Address cross paths. Data Cross Paths ? Data cross paths can also be referred to as register file cross paths. ? These cross paths allow operands from one side to be used by the other side. ? There are only two cross paths: ? one path which conveys data from side B to side A, 1X. ? one path which conveys data from side A to side B, 2X. ? Data cross paths only apply to the .L, .S and .M units. ? The data cross paths are very useful, however there are some limitations in their use. Data Cross Paths Data Cross Path Limitations A 2x .L1 .M1 .S1 B 1x src src dst (1) The destination register must be on same side as unit. (2) Source registers up to one cross path per execute packet per side. Execute packet: group of instructions that execute simultaneously. eg: ADD .L1x A0,B2,A2 MPY .M1x A0,B6,A9 SUB .S1x A8,B2,A8 || ADD .L1x A0,B0,A2 || Means that the SUB and ADD belong to the same fetch packet, therefore execute simultaneously. A 2x .L1 .M1 .S1 B 1x src src dst Data Cross Path Limitations eg: ADD .L1x A0,B2,A2 MPY .M1x A0,B6,A9 SUB .S1x A8,B2,A8 || ADD .L1x A0,B0,A2 NOT VALID! Data Cross Path Limitations A 2x .L1 .M1 .S1 B 1x src src dst Data Cross Paths for both sides A 2x .L1 .M1 .S1 B 1x src src dst .L2 .M2 .S2 dst src src Address cross paths .D1 A Addr