【正文】 wn values and mispares were transmitted along with relevant register information. Registers – This test loaded each of four (0,1,2,3) banks of generalpurpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls generalpurpose register bank selection. Generalpurpose register banks were then pared with their expected values. All mispares were corrected and error information was transmitted. Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly pared the learned value with the current one. Mispares were reloaded with learned value and error information was transmitted. Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information. VII. TEST METHODOLOGY The DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with Boot/Serial Loader code. This code initialized the DUT Computer and interface through a serial connection to the controlling puter, the Test Controller. The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms)。C and at a clock speeds of MHz to 24 MHz. They are manufactured in Intel’s CHMOS IIIE process. The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from to Volts over 0 to 70 176。Validation and Testing of Design Hardening for Single Event Effects Using the 8051 Microcontroller Abstract With the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using nondedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAμE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two mercial 8051 devices. Index Terms Single Event Effects, HardenedByDesign, microcontroller, radiation effects. I. INTRODUCTION NASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiationhardened microelectronic devices that are often two or more generations of performance behind mercial stateoftheart technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of mercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardenedbydesign (HBD).Building customtype HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely, costeffective, and reliable manner. However, one question still exists: traditional radiationhardened devices have lot and/or wafer radiation qualification tests performed。 what types of tests are required for HBD validation? II. TESTING HBD DEVICES CONSIDERATIONS Test methodologies in the United States exist to qualify individual devices through standards and anizations such as ASTM, JEDEC, and MILSTD 883. Typically, TID (Co60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices? As opposed to a “regular” mercialofftheshelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library? Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require plete radiation qualification testing? To answer this, other questions must be asked. How plete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived. Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of , is the data applicable to a 100 MHz operating frequency at ? Dynamic considerations (., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies. The point of the considerations is th