【正文】 resident on the DUT, was the boot code and serial code loader routines that established munications between the controller PC and the DUT. All test programs implemented: ? An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and munication to controller puter. ? An external realtime clock for data error tag. ? A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary. ? A foulup routine to reset program counter if it wanders out of code space. ? An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission. The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured. Interrupt – This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically pared to a known value. Unexpected values were transmitted with register information. Logic – This test performed a series of logic and math putations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All mispares of putations and expected results were transmitted with other relevant register information. Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and mispares were corrected while error information and register values were transmitted. Program Counter The program counter was used to continuously fetch constants at various offsets in the code. Constants were pared with known values and mispares were transmitted along with relevant register information. Registers – This test loaded each of four (0,1,2,3) banks of generalpurpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls generalpurpose register bank selection. Generalpurpose register banks were then pared with their expected values. All mispares were corrected and error information was transmitted. Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly pared the learned value with the current one. Mispares were reloaded with learned value and error information was transmitted. Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information. VII. TEST METHODOLOGY The DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with Boot/Serial Loader code. This code initialized the DUT Computer and interface through a serial connection to the controlling puter, the Test Controller. The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms)。C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized in order to maximize the similarity between the Dallas and Intel test codes. The CULPRiT technology device is a version of the MSC51 family patible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an onchip input/output signal levelshifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages。 文章所提到的 8051單片機(jī)核心是根據(jù) 美國航天局的高級微電子研究所（ IAμ E）的 CMOS超低功耗輻射容錯技術(shù)（ CULPRiT） 設(shè)計 的。 但是，仍然存在一個問題：常規(guī)輻射加固器件有許多和 /或硅片輻射條件測試 ， 加固工藝的驗證需要哪些類型的試驗？ 二 加固工藝檢測設(shè)備的考慮 美國的測試技術(shù)是要使單個器件通過如 ASTM ， JEDEC的，和 MIL STD – 883等的標(biāo)準(zhǔn)和組織的測試。 另外， 其他考慮因素還包括運作速度和工作電壓。微控制器是一個這樣的工具，正在深入量化抗輻射固化的改進(jìn)。這些是與 Aeroflex聯(lián)合技術(shù)微電子中心（ UTMC ）完全不同的方法 ，抗輻射固化的 8051的工業(yè)供應(yīng)商，利用抗輻射固化進(jìn)程研制自己的 8051單片機(jī)。 四 測試裝置 這一試驗的評價使用了三款器件。他們的額定電壓從 ,溫度在 0到 70 176。 C8051是 ROMless與 MSC 51系列指令系統(tǒng)兼容的。 1赫茲信號源為被測設(shè)備提供了一個外部看門狗定時信號，其看門狗輸出是通過一個示波器監(jiān)測。還可以制定和補(bǔ)充額外的測試，而不會影響整體測試設(shè)計。每一個軟件測試使用簡要介紹如下： 中斷 這項測試用到 6個可用中斷矢量圖中的 4個來觸發(fā)例程（串行，外部，定時器 0溢出，以及定時器 1溢出），累加器定期地與一個已知值比較，然后啟動例行程序順序地修改累加器的值。 寄存器 這項測試程序裝在中的四（ 0,1,2,3 ）段的通用寄存器或者 0xAA （段0和 2 ）或 0x55 （段 1和 3 ） 。 七 測試 方法 通過執(zhí)行位于地址 0x0000指令代碼來啟動被測設(shè)備計算機(jī)。如果SEFI發(fā)生，測試控制器強(qiáng)制重新啟動到開機(jī) /串行裝入程序代碼然后執(zhí)行后的測試功能。電路工作在 5, ， CMOS超低功耗輻射容錯 電路也是可以的。 在兩個有效的線 性能量轉(zhuǎn)移值， MeVcm2/mg 時， CMOS超低功耗輻射容錯 CCSDS無損壓縮芯片 ,SEU截面數(shù)據(jù) [ 7 ]作為一個頻率的函數(shù)。小心地把雙重敏感節(jié)點單粒子防護(hù)技術(shù)元件分開，但組合邏輯路徑的自動布線要與雙敏感節(jié)點足夠接近。本文討論了所用到的測試方法并提出了一種比較方法，通過采集數(shù)據(jù)比較工業(yè)技術(shù)與 CMOS超低功耗輻射容錯技術(shù)。