【正文】 LPRiT technologies based on the data taken. The CULPRiT devices consistently show significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the mercial devices. Additionally, theory is presented, based on the CULPRiT technology, that explain these results. This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a realworld device structure (., not just a test chip), and paring results to equivalent mercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application. ACKNOWLEDGEMENTS The authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA). 使用 8051單片機(jī)驗(yàn)證和測試單粒子效應(yīng)的加固工藝 摘要 隨著 代工業(yè)務(wù) （ 抗輻射加固設(shè)計(jì)的 芯片制造加工廠 專門 從事 的 一項(xiàng)業(yè)務(wù)） 的減少，使用非專用代工業(yè)務(wù) 的 新技術(shù)逐步發(fā)展起來。s memory space). Upon awaking from the reset, the DUT puter again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code. The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer39。 the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instruction set patible with the MSC51 family. V. TEST HARDWARE The 8051 Device Under Test (DUT) was tested as a ponent of a functional puter. Aside from DUT itself, the other ponents of the DUT puter were removed from the immediate area of the irradiation beam. A small card (one per DUT package type) with a unique hardwired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This DUT Board was connected to the Main Board by a short 60conductor ribbon cable. The Main Board had all other ponents required to plete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and munications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for manding of the DUT, downloading DUT Code to the DUT, and realtime error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup. VI. TEST SOFTWARE The 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT puter. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established munications between the controller PC and the DUT. All test programs implemented: ? An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and munication to controller puter. ? An external realtime clock for data error tag. ? A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary. ? A foulup routine to reset program counter if it wanders out of code space. ? An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission. The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured. Interrupt – This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically pared to a known value. Unexpected values were transmitted with register information. Logic – This test performed a series of logic and math putations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All mispares of putations and expected results were transmitted with other relevant register information. Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and mispares were corrected while error information and register values were transmitted. Program Counter The program counter was used to continuously fetch constants at various offsets in the code. Constants were pared with kno