【正文】 ed by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations. III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLER With their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAμE (the focus of this study). As these HBD technologies bee available, validation of the technology, in the natural space radiation environment, for NASA’s use in spaceflight systems is required. The 8051 microcontroller is an industry standard architecture that has broad acceptance, wideranging applications and development tools available. There are numerous mercial vendors that supply this controller or have it integrated into some type of systemonachip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by AeroflexUnited Technologies Microelectronics Center (UTMC), the mercial vendor of a radiation– hardened 8051, that built their 8051 microcontroller using radiation hardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation. The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard 8051 mercial device from Intel and a version using stateoftheart processing from Dallas Semiconductor. By performing this sidebyside parison, the cost benefit, performance, and reliability trade study can be done. In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as plete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more plete understanding of how to test plex structures, such as microcontrollers, and how to more efficiently test these structures in the future. IV. TEST DEVICES Three devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a mercial 8051, manufactured by Intel and Dallas Semiconductor, respectively. The Intel devices are the ROMless, CMOS version of the classic 8052 MCS51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 176。 一 導言 美國航天局要在空間輻射環(huán)境中最低限度地使用資源條件下，不斷努力提供最好科學方法 [ 1,2 ] 。 需要考慮的因素是，設計程序庫，測試范圍，鑄造特點必須是已知的，并且深刻理解測試用途 。商業(yè)研究一 一比較了他們的成本效益，性能和可靠性。此外，重新設計技術核心，最終使該機器周期縮短，從而得到有效的處理能力，這大約是 （快）比標準的 8052器件。它的目的是要作為一個模 塊化設計，為被測設備的每一個具體部分的設計一系列小型試驗程序 。計算和期望值的所有不匹配與其他有關寄存器信息一起傳送。被測設備計算機下載測試代碼并把它放入程序代碼存儲器（位于被測設備計算機主板） 。但是，考慮到實用的回偏電壓，電壓可以超過現在的額定電壓。 此外，第二個 SEU機制，開始約 4060線性能量轉移，收集足夠多的干擾，能夠有效地翻轉的 單粒子防護技術元件的 冗余存儲節(jié)點倍數。通過在器件結構（即，不只是一個測試芯片）應用 HBD技術 ，以及等價商業(yè)設備比較結果， 人們可以有信心在這一的硬度水平將可從該技術在任何硬件設計電路應用。思路是多余的輸入數據是由一個總的重復組合邏輯（稱為“雙軌設計” ）提供， 這樣一個防護上簡單的 SET就不能產生翻轉。 八 討論 為什么 CMOS超低功耗輻射容錯 設備不發(fā)生閉鎖現象，主要原因是 作電壓低于閉鎖發(fā)生需要的額定電壓。 不匹配與已知值和錯誤信息被重新裝入。 ? “混亂”的例行程序，如果它偏離代碼空間就會重置 程序計數器。各主板的所有其他組件需要被測設備計算機完成，包括在一些設計名義上是沒有必要的組件（如外部內存，外部 ROM和地址鎖存器） 。C ，時鐘頻率為 24兆赫。醫(yī)學研究理事會和 高級微電子研究所 都選擇這個設備，但他們論證的是兩種截然不同固化工藝。這是否需要完成輻射條件測試？回答這個問題之前，先看一下其他的問題。s fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of binational logic (referred to as “dual rail design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated placeandroute of the binatorial logic paths may have placed dual sensitive nodes close enough. At this point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the binatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 4060 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this μm library, the node separation is several microns. However, since it takes less charge to upset a node operating at Volts, with transistors having effective thresholds around 70 mV, this is likely the effect