【正文】 dor of a radiation– hardened 8051, that built their 8051 microcontroller using radiation hardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation. The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard 8051 mercial device from Intel and a version using stateoftheart processing from Dallas Semiconductor. By performing this sidebyside parison, the cost benefit, performance, and reliability trade study can be done. In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as plete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more plete understanding of how to test plex structures, such as microcontrollers, and how to more efficiently test these structures in the future. IV. TEST DEVICES Three devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a mercial 8051, manufactured by Intel and Dallas Semiconductor, respectively. The Intel devices are the ROMless, CMOS version of the classic 8052 MCS51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 176。C and at a clock speeds of MHz to 24 MHz. They are manufactured in Intel’s CHMOS IIIE process. The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from to Volts over 0 to 70 176。C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized in order to maximize the similarity between the Dallas and Intel test codes. The CULPRiT technology device is a version of the MSC51 family patible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an onchip input/output signal levelshifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages。 the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instruction set patible with the MSC51 family. V. TEST HARDWARE The 8051 Device Under Test (DUT) was tested as a ponent of a functional puter. Aside from DUT itself, the other ponents of the DUT puter were removed from the immediate area of the irradiation beam. A small card (one per DUT package type) with a unique hardwired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This DUT Board was connected to the Main Board by a short 60conductor ribbon cable. The Main Board had all other ponents required to plete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and munications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for manding of the DUT, downloading DUT Code to the DUT, and realtime error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup. VI. TEST SOFTWARE The 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT puter. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established munications between the controller PC and the DUT. All test programs implemented: ? An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and munication to controller puter. ? An external realtime clock for data error tag. ? A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary. ? A foulup routine to reset program counter if it