電氣專業(yè)畢業(yè)設(shè)計(jì)外文文獻(xiàn)與中文翻譯-展示頁
2024-12-14 04:41本頁面
【正文】 ocessors and peripherals in addition a set of predefined core devices OPP. OPP software in accordance with an external regulator is required to send control signals to set the minimum voltage. For example, DVFS apply to the two supply voltage VDD1 (DSP and ARM processors supply voltage) and VDD2 (peripheral subsystems interconnection and power supply voltage), the two voltage rails to provide the majority of chip power ( usually 75% to 80%). In the implementation of MP3 decoder, the DSP processor can be transferred to lowperformance point, thus greatly reducing the power consumption for other tasks, when the ARM operating frequency up to 125 MHz. In order to achieve the best power necessary functionality, we VDD1 can be reduced to volts instead of the maximum voltage of volts to ensure that the working frequency of 600 MHz. Adaptive voltage scaling (AVS) as a second active power management technology, based on the chip manufacturing process, as well as the life cycle of device operation generated based on the difference. The technology and all processors share the same preprogrammed different DVFS the OPP. It can be inferred that the majority of the manufacturing process has matured, the chip39。s cool device in the frequency of 125 MHz need to volts, while the hot device in the frequency of only volts. Adaptive voltage scaling (AVS) technology uses the corresponding feedback loop supply voltage regulator to ensure that all devices running tasks in a specific frequency required Software can work for each OPP set up AVS hardware, and control algorithms through I2C bus to send mands to external voltage regulator in order to gradually reduce the output of the appropriate regulator, until just over the target processor frequency requirement. For example, developers can design a first to meet all of the voltage, frequency of 125 MHz at volts (in Figure 1 in the top of the V1). However, if the system using AVS technology to insert the hot device, then the feedback mechanism onchip ARM will automatically be reduced to volts of the voltage or lower (V2 in Figure 1 above). The first two active power management technology can minimize the operating voltage so that a certain part of the device in the desired speed. In contrast, the third method Dynamic power switching (DPS) to determine the device when it can plete the calculation of the current task, if no need, then allow the device to enter lowpower standby mode (Figure 2). For example, the processors are waiting for DMA transfer to plete the process will enter a lowpower state. Processor in a few microseconds after the wakeup call will be able to return to normal working condition.Figure 2 Dynamic power switching (DPS) in a given part of a device after the pletion of the task to enter the lowpower state Passive power management Although the DPS will allow multimedia systemonchip (SoC) as part of entering the lowpower state, but in some cases, we can have the entire device into the low power mode in the absence of the application to run automatically or through user requests access to lowpower. To
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