【正文】 nging market needs, can be handled with appropriately placed FPGA cores. The question must be asked: why embed FPGA into an ASIC if a two chips solution could achieve the same results? The answer is both technical and economic. Technically, for a certain class of applications, the embedded solution offers greater performance with lower power dissipation. By embedding the FPGA into the ASIC, signals that must propagate from the ASIC through the FPGA, then back to the ASIC can avoid four chip boundary delays, two card crossings, and the associated power dissipation. By keeping the ASIC to FPGA interconnections on the die, valuable ASIC I/O pins are also conserved. Economically, the embedded solution can be the less expensive option. As we will discuss, the FPGA fabric does not require any unique semiconductor processing above and beyond the base ASIC (unlike embedded flash or embedded DRAM). The resulting increase in ASIC cost is associated with the area occupied by the embedded FPGA core. In addition, the cost of assembly, test and packaging of a secong chip are eliminated. In certain cases, it can be advantageous to include embedded FPGA on an ASIC if that FPGA eliminates the need for additional design passes. For example, at volumes of up to 250000 pieces, 50K gates of embedded FPGA are cost effectives. Similarly, 10K gates of embedded FPGA are cost effective versus a 2 pass ASIC design at volume of up to 1M. In general, if mask costs rise, volumes decrease, or more design passes are avoided, then the embedded FPGA approach bees progressively more costeffective pared to the ASIC approach. This is because at low volumes, the mask costs (and NRE) for additional design passes bees a significant adder to perchip cost, and this can outweigh the cost impact of the larger die area required by the embedded FPGA circuitry. This analysis leads us to conclude that technology and market trends have created a need for the development of the hybrid ASIC/FPGA product. Mask costs for advanced technologies are growing – marking multiple design passes too costly for many applications. Fortunately, the technology advancements that have driven this trend have also opened up the potential to embed significant amounts of FPGA gates onto an ASIC die – enough to handle some of the design updates that would otherwise require additional design passes.10．4 Hybrid Offering Overview The IBM/Xilinx hybrid will first be available in IBM’s Cu08 90nm ASIC offering, and will consist of three FPGA block sizes. Multiple blocks used can be mixed and matched. Physically, the FPGA cores are being ported to the same semiconductor process that the ASIC product uses. The issues encountered in doing this porting are similar to those of other 3rd party IP ports. One of the largest challenges is full chip physical verification. Common design rules and transistor design points are critical in blending of IP between suppliers. Minor difference in design rules can be acmodated, assuming that checking decks and other verification software are able to handle the mixture of design rules. Designing these tools for increased flexibility will likely be needed as more panies share IP. To ensure that the FPGA can be integrated with the rest of the ASIC power, agreement must be reached on metal stack options. In the case of the Cu08 hybrid offering,5 level of metal were allocated to the FPGA blocks. This requires a relayout of the FPGA cores, which were originally designed for a standard product with 9 levels of metal. As part of the relayout, the power distribution of the FPGA blocks will be designed to integrate easily into the ASIC power distribution methodology. Care needs to be taken to ensure the power density required by the FPGA blocks are within the capability of the ASIC power supply routing. Due to extensive use of passgate structures, the FPGA blocks require standard levels, while the bulk of the chip operates at lower levels.The embedded FPGA blocks consist of programmable logic blocks, configuration logic, test interface logic, and simplified IO buffers for use in driving and receiving onchip nets. Multiple end user configuration mode are supported including FPGA, serial and parallel modes. Individual cores can be configured asynchronously, allowing for “onthefly” reconfiguration.To design the new hybrid chips, a modified design methodology is being developed as shown in Figure . This hybrid design flow incorporates two proven design methodologies, the IBM ASIC flow and the XILINX FPGA flow, including several third party vendor synthesis options. The ASIC methodology integrates the embedded FPGA as a hard core with appropriate ASIC label models. The FPGA flow, including timing closure of the FPGA configuration, is done using XILINX tools, the designer has the choice of using constraints or detailed