【正文】 timing from the Xilinx tool flow to close the ASIC timing at the FPGA cote interfaces. If an FPGA configuration is known prior to the design of the ASIC, actual timing information can be passed to the ASIC tools from the FPGA tools. If the logic content of the embedded FPGA is unknown, the ASIC design can be pleted using timing assertions and the embedded FPGA design can be pleted later. If the embedded FPGA design is being reconfigured after the ASIC is in manufacturing, the final timing constraints from the pleted ASIC can be passed to the FPGA tools for the new FPGA design.The logic design of the chip must be partitioned prior to final synthesis. The logic destined for an FPGA block is processed independently of the logic design for ASIC logic .When multiple FPGA logic are used ,each must be designed and optimized independently.The logical design of the chip must be partitioned prior to final synthesis. The logic destined for an FPGA block is processed independently of the logic destined for ASIC logic. When multiple FPGA logic blocks are used, each must be designed and optimized independently.The ASIC physical design process treats the FPGA macro similarly to other large place able objects, except for port assignment. During the initial ASIC design, the port assignment of each embedded FPGA block can be modified to acmodate floor planning or timing requirements. Once the final ASIC design is tapeout ,the port assignments are fixed of subsequent FPGA configurations.The IBM ASIC methodology has been described in references, and the Xilinx FPGA methodology is described in reference. As to be expected, most of the issues in cresting the hybrid methodology occur at the boundary between the two methodologies. The mechanics of the munications between the two stems can be acplished by creating data translators, however, optimization between the two systems can be difficult, due to the significant architectural differences between traditional ASIC flows and traditional FPGA flows. ASIC和FPGA的混合系統(tǒng)FPGA是英文FieldBecause piles with VHDL the execution software interior to each group of digital quantity is according to the parallel processing, moreover the FPGA hardware speed is the ns level, this is a speed which current any MCU all with difficulty achieved, therefore this system pared to other systems can realtime, monitor the signal quantity fast the change。But when in the system must gather the signal quantity are specially many when (is specially each kind of signal quantity, condition quantity), depends on merely with the ordinary MCU resources on often with difficulty pletes the task。 The serial pattern may use serial PROM to program FPGA。英文資料及中文翻譯A hybrid ASIC and FPGA ArchitectureFPGA is English Field Programmable Gate Array abbreviation, namely the scene programmable gate array, it is the product which in PAL, GAL, EPLD and so on in the programmable ponent foundation further develops. It is took in the specialpurpose integrated circuit (ASIC) domain one kind partly has custommade, both solves has had custommade the electric circuit which the electric circuit appears the insufficiency, and has overe the original programmable ponent gate number limited shorting. FPGA used logical unit array LCA (Logic Cell Array) this kind of new concept, the interior including has been possible to dispose logical module CLB (Configurable Logic Block), output load module IOB (Input Output Block) and internal segment (Interconnect) three parts. The FPGA essential feature mainly has:1) Uses FPGA to design the ASIC electric circuit, the user does not need to throw the piece production, can obtain the chip which es in handy. 2) FPGA may make other all to have custommade or partly to have custommade the ASIC electric circuit the experimental preview.2) The FPGA interior has the rich trigger and the I/O pin. 3) FPGA is in the ASIC electric circuit designs the cycle to be shortest, the development cost is lowest, one of risk smallest ponents.4) FPGA is in the ASIC electric circuit designs the cycle to be shortest, the development cost is lowest, one of risk smallest ponents.5) FPGA uses the high speed CHMOS craft, the power loss is low, may and CMOS, the TTL level is patible. 　 It can be said that, the FPGA chip is the small batch system enhances the system integration rate, one of reliable best choices. FPGA is by deposits the procedure establishes its active status in internal RAM, therefore, time work needs to carry on the programming to internal RAM .The user may act according to the different disposition pattern, selects the different programming method. 　When adds the electricity, the FPGA chip the data readin internal programs EPROM in RAM, after the disposition pletes, FPGA thrust buildup .After falls the electricity, FPGA restores the unsoldered glass,