【正文】 endmodule Once the stimulus block is pleted, we are ready to run the simulation and verify the functional correctness of the design block. The output obtained when stimulus and design blocks are simulated is shown 0 Output q = 0 20 Output q = 1 30 Output q = 2 40 Output q = 3 50 Output q = 4 60 Output q = 5 70 Output q = 6 80 Output q = 7 90 Output q = 8 100 Output q = 9 110 Output q = 10 120 Output q = 11 130 Output q = 12 140 Output q = 13 150 Output q = 14 160 Output q = 15 170 Output q = 0 180 Output q = 1 190 Output q = 2 195 Output q = 0 210 Output q = 1 220 Output q = 2 Summary In this chapter we discussed the following concepts. ? Two kinds of design methodologies are used for digital design: topdown and bottomup. A bination of these two methodologies is used in today39。 20 $finish。 10 reset = 139。 180 reset = 139。 15 reset = 139。 //toggle clk every 5 time units // Control the reset signal that drives the design block // reset is asserted from 0 to 20 and from 200 to 220. initial begin reset = 139。b0。 ripple_carry_counter r1(q, clk, reset)。 reg reset。 the reset signal stays up from time 0 to 15 and then goes up again from time 195 to 205. Output q counts from 0 to 15. module stimulus。 else q = d。 // Lots of new constructs. Ignore the functionality of the // constructs. // Concentrate on how the design block is built in a topdown fashion. always (posedge reset or negedge clk) if (reset) q = 139。 input d, clk, reset。 // not is a Verilogprovided primitive. case sensitive endmodule ? Since T_FF instantiates D_FF, we must now define the internals of module D_FF. We assume asynchronous reset for the D_FFF. module D_FF(q, d, clk, reset)。 D_FF dff0(q, d, clk, reset)。 input clk, reset。 endmodule ? In the above module, four instances of the module T_FF (Tflipflop) are used. Therefore, we must now define the internals of the module T_FF module T_FF(q, clk, reset)。 T_FF tff2(q[2],q[1], reset)。 //4 instances of the module T_FF are created. T_FF tff0(q[0],clk, reset)。 output [3:0] q。 module T_FF(q, clock, reset)。 output [3:0] q。 // Instantiate D_FF. Call it dff0. not n1(d, q)。 wire d。 output q。 T_FF tff3(q[3],q[2], reset)。 T_FF tff1(q[1],q[0], reset)。 //I/O signals and vector declarations input clk, reset。 ... functionality of Tflipflop ... endmodule Verilog is both a behavioral and a structural language. Internals of each module can be defined at four levels of abstraction, depending on the needs of the design. The module behaves identically with the external environment irrespective of the level of abstraction at which the module is described. The internals of the module are hidden from the environment. Thus, the level of abstraction to describe a module can be changed without any change in the environment. Levels of abstraction Behavioral or algorithmic level This is the highest level of abstraction provided by Verilog HDL. A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details. Designing at this level is very similar to C programming. Dataflow level At this level, the module is designed by specifying the data flow. The designer is aware of how data flows between hardware registers and how the data is processed in the design. Gate level The module is implemented in terms of logic gates and interconnections between these gates. Design at this level is similar to describing a design in terms of a gatelevel logic diagram. Switch level This is the lowest level of abstraction provided by Verilog. A module can be implemented in terms of switches, storage nodes, and the interconnections between them. Design at this level requires knowledge of switchlevel implementation details. Four levels of abstraction levels of abstraction (why) Verilog allows the designer to mix and match all four levels of abstractions in a design ? In the digital design munity, the term register transfer level (RTL) is frequently used for a Verilog description that uses a bination of behavioral and dataflow constructs and is acceptable to logic synthesis tools. ? If a design contains four modules, Verilog allows each of the modules to be written at a different level of