eda技術(shù)第16-18講-資料下載頁(yè)
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【正文】 hich is the ripple carry counter. module ripple_carry_counter(q, clk, reset)。 output [3:0] q。 input clk, reset。 //4 instances of the module T_FF are created. T_FF tff0(q[0],clk, reset)。 T_FF tff1(q[1],q[0], reset)。 T_FF tff2(q[2],q[1], reset)。 T_FF tff3(q[3],q[2], reset)。 endmodule ? In the above module, four instances of the module T_FF (Tflipflop) are used. Therefore, we must now define the internals of the module T_FF module T_FF(q, clk, reset)。 output q。 input clk, reset。 wire d。 D_FF dff0(q, d, clk, reset)。 not n1(d, q)。 // not is a Verilogprovided primitive. case sensitive endmodule ? Since T_FF instantiates D_FF, we must now define the internals of module D_FF. We assume asynchronous reset for the D_FFF. module D_FF(q, d, clk, reset)。 output q。 input d, clk, reset。 reg q。 // Lots of new constructs. Ignore the functionality of the // constructs. // Concentrate on how the design block is built in a topdown fashion. always @(posedge reset or negedge clk) if (reset) q = 139。b0。 else q = d。 Endmodule All modules have been defined down to the lowestlevel leaf cells in the design methodology. The design block is now plete. Stimulus Block ? We must now write the stimulus block to check if the ripple carry counter design is functioning correctly. ? In this case, we must control the signals clk and reset so that the regular function of the ripple carry counter and the asynchronous reset mechanism are both tested. ? We use the waveforms shown below to test the design. Waveforms for clk, reset, and 4bit output q are shown. The cycle time for clk is 10 units。 the reset signal stays up from time 0 to 15 and then goes up again from time 195 to 205. Output q counts from 0 to 15. module stimulus。 reg clk。 reg reset。 wire[3:0] q。 ripple_carry_counter r1(q, clk, reset)。 // instantiate the design block // Control the clk signal that drives the design block. Cycle time = 10 initial clk = 139。b0。 //set clk to 0 always 5 clk = ~clk。 //toggle clk every 5 time units // Control the reset signal that drives the design block // reset is asserted from 0 to 20 and from 200 to 220. initial begin reset = 139。b1。 15 reset = 139。b0。 180 reset = 139。b1。 10 reset = 139。b0。 20 $finish。 //terminate the simulation end // Monitor the outputs initial $monitor($time, Output q = %d, q)。 endmodule Once the stimulus block is pleted, we are ready to run the simulation and verify the functional correctness of the design block. The output obtained when stimulus and design blocks are simulated is shown 0 Output q = 0 20 Output q = 1 30 Output q = 2 40 Output q = 3 50 Output q = 4 60 Output q = 5 70 Output q = 6 80 Output q = 7 90 Output q = 8 100 Output q = 9 110 Output q = 10 120 Output q = 11 130 Output q = 12 140 Output q = 13 150 Output q = 14 160 Output q = 15 170 Output q = 0 180 Output q = 1 190 Output q = 2 195 Output q = 0 210 Output q = 1 220 Output q = 2 Summary In this chapter we discussed the following concepts. ? Two kinds of design methodologies are used for digital design: topdown and bottomup. A bination of these two methodologies is used in today39。s digital designs. As designs bee very plex, it is important to follow these structured approaches to manage the design process. ? Modules are the basic building blocks in Verilog. Modules are used in a design by instantiation. An instance of a module has a unique identity and is different from other instances of the same module. Each instance has an independent copy of the internals of the module. It is important to understand the difference between modules and instances. ? There are two distinct ponents in a simulation: a design block and a stimulus block. A stimulus block is used to test the design block. The stimulus block is usually the toplevel block. There are two different styles of applying stimulus to a design block. ? The example of the ripple carry counter explains the stepbystep process of building all the blocks required in a simulation. This chapter is intended to give an understanding of the design process and how Verilog fits into the design process. The details of Verilog syntax are not important at this stage and will be dealt with in later chapters.
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