eda技術(shù)與應(yīng)用講義第2章eda設(shè)計流程及其工具-資料下載頁
2025-01-12 18:07本頁面
【正文】 vice(s), in the form of one or more POFs, SOFs, Hex Files, TTFs, Jam Files, JBC Files, and/or JEDEC Files. POFs and JEDEC Files are always generated。 SOFs, Hex Files, and TTFs are always generated if the project uses ACEX 1K, FLEX 6000, FLEX 8000 or FLEX 10K devices。 and Jam Files and JBC Files are always generated for MAX 9000, MAX 7000B, MAX 7000AE or MAX 3000A projects. If you turn on the Enable JTAG Support option in the Classic amp。 MAX Global Project Device Options dialog box (Assign menu) or the Classic amp。 MAX Individual Device Options dialog box, the Assembler will also generate Jam Files and JBC Files for MAX 7000A or MAX 7000S projects. After pilation, you can also use SOFs to create different types of files for configuring FLEX 6000, FLEX 8000 and FLEX 10K devices with Convert SRAM Object Files (File menu). ? The programming files can then be processed by the MAX+PLUS II Programmer and the MPU or APU hardware to produce working devices. Several other programming hardware manufacturers also provide programming support for Altera devices. ? 返回 Simulation Mode ? Functional ? Simulates the behavior of flattened lists extracted from the design files. You can use Tcl mands and scripts to control simulation and to provide vector stimuli. You can also provide vector stimuli in a Vector Waveform File (.vwf) or a textbased Vector File (.vec), although the Simulator uses only the sequence of logic level changes, and not their timing, from the vector stimuli. This type of simulation also allows you to check simulation coverage (the ratio of output ports actually toggling between 1 and 0 during simulation, pared to the total number of output ports present in the list). ? Timing ? Uses a fully piled list that includes estimated or actual timing information. You can use Tcl mands and scripts to control simulation and to provide vector stimuli. You can also provide vector stimuli in a Vector Waveform File (.vwf) or a textbased Vector File (.vec). This type of simulation also allows you to check setup and hold times, detect glitches, and check simulation coverage (the ratio of output ports actually toggling between 1 and 0 during simulation, pared to the total number of output ports present in the list). ? Timing using Fast Timing Model ? Performs a timing simulation using the Fast Timing Model to simulate fastest possible timing conditions with the fastest device speed grade
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