【正文】 clk = ~clk。 有關(guān) Verilog HDL的幾個重要基本概念 1) 綜合： 通過工具把用 Verilog HDL描述的模塊自動轉(zhuǎn)換為用門級電路網(wǎng)表表示的模塊的過程。 3) Verilog HDL測試模塊 ： 用 Verilog HDL描述的模塊，可以用來產(chǎn)生測試信號序列并可以接收被測試模塊的信號，用于驗(yàn)證所設(shè)計(jì)的模塊是否能正常運(yùn)行，往往不可綜合成具體門級電路。 Verilog174。 ... functionality of Tflipflop ... endmodule Verilog is both a behavioral and a structural language. Internals of each module can be defined at four levels of abstraction, depending on the needs of the design. The module behaves identically with the external environment irrespective of the level of abstraction at which the module is described. The internals of the module are hidden from the environment. Thus, the level of abstraction to describe a module can be changed without any change in the environment. Levels of abstraction Behavioral or algorithmic level This is the highest level of abstraction provided by Verilog HDL. A module can be implemented in terms of the desired design algorithm without concern for the hardware implementation details. Designing at this level is very similar to C programming. Dataflow level At this level, the module is designed by specifying the data flow. The designer is aware of how data flows between hardware registers and how the data is processed in the design. Gate level The module is implemented in terms of logic gates and interconnections between these gates. Design at this level is similar to describing a design in terms of a gatelevel logic diagram. Switch level This is the lowest level of abstraction provided by Verilog. A module can be implemented in terms of switches, storage nodes, and the interconnections between them. Design at this level requires knowledge of switchlevel implementation details. Four levels of abstraction levels of abstraction (why) Verilog allows the designer to mix and match all four levels of abstractions in a design ? In the digital design munity, the term register transfer level (RTL) is frequently used for a Verilog description that uses a bination of behavioral and dataflow constructs and is acceptable to logic synthesis tools. ? If a design contains four modules, Verilog allows each of the modules to be written at a different level of abstraction. ? As the design matures, most modules are replaced with gatelevel implementations. Normally, the higher the level of abstraction, the more flexible and technologyindependent the design. ? As one goes lower toward switchlevel design, the design bees technologydependent and inflexible. ? A small modification can cause a significant number of changes in the design. ? Consider the analogy with C programming and assembly language programming. It is easier to program in a higherlevel language such as C. The program can be easily ported to any machine. However, if you design at the assembly level, the program is specific for that machine and cannot be easily ported to another machine. Instances A module provides a template from which you can create actual objects. When a module is invoked, Verilog creates a unique object from the template. Each object has its own name, variables, parameters, and I/O interface. The process of creating objects from a module template is called instantiation, and the objects are called instances. In Example 21, the toplevel block creates four instances from the Tflipflop (T_FF) template. Each T_FF instantiates a D_FF and an inverter gate. Each instance must be given a unique name. Example 21 Module Instantiation module ripple_carry_counter(q, clk, reset)。 T_FF tff1(q[1],q[0], reset)。 output q。 // Instantiate D_FF. Call it dff0. not n1(d, q)。 module T_FF(q, clock, reset)。 //4 instances of the module T_FF are created. T_FF tff0(q[0],clk, reset)。 endmodule ? In the above module, four instances of the module T_FF (Tflipflop) are used. Therefore, we must now define the internals of the module T_FF module T_FF(q, clk, reset)。 D_FF dff0(q, d, clk, reset)。 input d, clk, reset。 else q = d。 reg reset。b0。 15 reset = 139。 10 reset = 139。 endmodule Once the stimulus block is pleted, we are ready to run the simulation and verify the functional correctness of the design block. The output obtained when stimulus and design blocks are simulated is shown 0 Output q = 0 20 Output q = 1 30 Output q = 2 40 Output