verilog硬件描述語(yǔ)言基礎(chǔ)(參考版)
2025-07-20 18:50本頁(yè)面
【正文】 Partitioning for Synthesis Objective ?Better Synthesis Results ? Faster Compile Runtimes ? Ability to Use Simple Strategy to meet Timing Constraints ? Optimal Design Partitioning for Synthesis Guidelines ?Register all output signals of the module ? Separate modules that have different design goals ? Complete binational logic paths in a single module, and specially avoid glue logic ? Considering resource sharing ? Separate asychronous logic from synchronous logic ? Separate blocks controlled by different clocks ?Separate memory from random logic Partitioning for Synthesis Register all output signals of the module Comb.LogicComb.LogicClkComb.LogicClkComb.LogicComb.LogicClkPartitioning for Synthesis Separate modules that have different design goals CriticalPaths LogicclkNoncriticalpaths logicclkNoncriticalpaths logicclkCriticalPaths LogicclkBad Partition Better PartitionPartitioning for Synthesis binational logic paths in a single module AComb.Logic AComb.Logic BComb.Logic CBad PartitionPartitioning for Synthesis AComb.Logic AComb.Logic BBetter PartitionComb.Logic CPartitioning for Synthesis ClockGenerationSubmodule 1Submodule 2Submodule kclk1clk2clk3TOP LEVELClock Generation Circuits is isolated at the top levelPartitioning for Synthesis FSM Partition Objective: High performance Method: ?Cascade partition ?MasterSlave Partition Partitioning for Synthesis Data INControl Path (FSM)Data PathInputControlSignalsClk SignalsData_OutControlSignalsOutputPartitioning for Synthesis Input Control SignalsCascade PartitionFSM1 FSM2 FSMnStartFSM2 StartFSMnControl signalsPartitioning for Synthesis InputControlSignalsOutputControlSignalsFSM1 FSM2 FSMnControl signalsMaster FSMStartFSM1StartFSM2 StartFSMnMaster_Slave Partition。always (posedge Clk or negedge rst)if (~rst) PS = Initial_state。 OUTPUT = h(PS, INPUT)。 ? posedge Clk : PS = NS。 end end end endCoding for Synthesis Out1010101010A[5]a[6]c[4]Ctrl_is_lateC[5]A[4]A[3]C[3]A[2]A[1]C[2]C[1]Coding for Synthesis 4 FSM描述 Mealy機(jī) ?NS = f( PS, INPUT)。 else begin if (C[5]) Out= A[6]。else begin if (~(C[4]amp。else begin if (C[2]) Out = A[2]。a = In 。c = b 。reg [BUS_SIZE1 :0] a,b,c,d。 endCoding for Synthesis input [BUS_SIZE1 :0] In。c = b 。always ( posedge Clk) begina = In 。input Clk 。d = c 。b = a 。reg [BUS_SIZE1 :0] a,b,c,d。 Coding for Synthesis input [BUS_SIZE1 :0] In。 ?對(duì)組合塊，每一個(gè) 出現(xiàn)在賦值語(yǔ)句右邊 且 沒(méi)有在塊內(nèi)被預(yù)先賦值 的信號(hào)應(yīng)列入表中； ??對(duì)時(shí)序塊， 1） 時(shí)鐘控制信號(hào) 必須出現(xiàn)在敏感表中； 2） 若為異步置 /復(fù)位 ，則相應(yīng)的置 /復(fù)位信號(hào)必須列入敏感表。b0。endelsebegind = e 。d = 139。elsed = e。 ? 避免條件置復(fù) /位； ? 時(shí)序邏輯器件的置復(fù) /位不應(yīng)放在 initial描述塊中（ 可綜合性、保證綜合前和綜合后的模擬結(jié)果相同 ） Coding for Synthesis Objective ?Performance ? Testability ? Synthesis ? Simplification and Timing Analysis ?保證綜合前、后的邏輯模擬結(jié)果的一致 Coding for Synthesis ? 時(shí)序元件問(wèn)題； ? always (敏感信號(hào) /變量表）完整性問(wèn)題； ? 組合電路的反饋問(wèn)題； ? Blocking/Nonblocking賦值語(yǔ)句的使用問(wèn)題； ? if…else/ case 描述的選擇； ? FSM的描述 Coding for Synthesis 1 時(shí)序元件問(wèn)題：
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