verilog硬件描述語(yǔ)言基礎(chǔ)-資料下載頁(yè)
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【正文】 edge Clk) begina = In 。b = a 。c = b 。d = c 。 endinput [BUS_SIZE1 :0] In。input Clk 。reg [BUS_SIZE1 :0] a,b,c,d。always @( posedge Clk) begina = In 。b = a 。c = b 。d = c 。 endCoding for Synthesis input [BUS_SIZE1 :0] In。input Clk 。reg [BUS_SIZE1 :0] a,b,c,d。always @( posedge Clk) begind = c 。c = b 。b = a 。a = In 。 endbcInadClkCoding for Synthesis 4 if…else 及其嵌套結(jié)構(gòu)與 case語(yǔ)句 ?盡量少用嵌套的 if…else 結(jié)構(gòu)； 級(jí)聯(lián)的二選一開(kāi)關(guān) ?采用 case、 casex、 casez結(jié)構(gòu) 多路選擇開(kāi)關(guān) if (~C[1])Out= A[1]。else begin if (C[2]) Out = A[2]。 else beginif (C[3]) Out=A[3]。else begin if (~(C[4]amp。Ctrl_is_late)) Out = A[4]。 else begin if (C[5]) Out= A[6]。 else Out = A[5]。 end end end endCoding for Synthesis Out1010101010A[5]a[6]c[4]Ctrl_is_lateC[5]A[4]A[3]C[3]A[2]A[1]C[2]C[1]Coding for Synthesis 4 FSM描述 Mealy機(jī) ?NS = f( PS, INPUT)。 ? OUTPUT = h(PS, INPUT)。 ? posedge Clk : PS = NS。 Coding for Synthesis 描述方式： 組合塊： always @(INPUT or PS ) begin NS = f (PS, INPUT)。 OUTPUT = h(PS, INPUT)。 end 時(shí)序塊： always @(posedge Clk)PS = NS。always @(posedge Clk or negedge rst)if (~rst) PS = Initial_state。else PS =NS。Partitioning for Synthesis Objective ?Better Synthesis Results ? Faster Compile Runtimes ? Ability to Use Simple Strategy to meet Timing Constraints ? Optimal Design Partitioning for Synthesis Guidelines ?Register all output signals of the module ? Separate modules that have different design goals ? Complete binational logic paths in a single module, and specially avoid glue logic ? Considering resource sharing ? Separate asychronous logic from synchronous logic ? Separate blocks controlled by different clocks ?Separate memory from random logic Partitioning for Synthesis Register all output signals of the module Comb.LogicComb.LogicClkComb.LogicClkComb.LogicComb.LogicClkPartitioning for Synthesis Separate modules that have different design goals CriticalPaths LogicclkNoncriticalpaths logicclkNoncriticalpaths logicclkCriticalPaths LogicclkBad Partition Better PartitionPartitioning for Synthesis binational logic paths in a single module AComb.Logic AComb.Logic BComb.Logic CBad PartitionPartitioning for Synthesis AComb.Logic AComb.Logic BBetter PartitionComb.Logic CPartitioning for Synthesis ClockGenerationSubmodule 1Submodule 2Submodule kclk1clk2clk3TOP LEVELClock Generation Circuits is isolated at the top levelPartitioning for Synthesis FSM Partition Objective: High performance Method: ?Cascade partition ?MasterSlave Partition Partitioning for Synthesis Data INControl Path (FSM)Data PathInputControlSignalsClk SignalsData_OutControlSignalsOutputPartitioning for Synthesis Input Control SignalsCascade PartitionFSM1 FSM2 FSMnStartFSM2 StartFSMnControl signalsPartitioning for Synthesis InputControlSignalsOutputControlSignalsFSM1 FSM2 FSMnControl signalsMaster FSMStartFSM1StartFSM2 StartFSMnMaster_Slave Partition
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鄂ICP備17016276號(hào)-1