【正文】 ,第二位C,第三位B,第四位a,第五位c,第六位b調(diào)用顯示程序, 第一位C,第二位A,第三位B,第四位a,第五位c,第六位b調(diào)用顯示程序,顯示EEE返回圖37(e) 120度電機(jī)判斷的主程序流程圖 其他子程序在系統(tǒng)的軟件設(shè)計(jì)過程中多次運(yùn)用了延時子程序和子程序1，下面對這兩個子程序進(jìn)行簡單介紹。子程序1的流程圖如下圖38所示，延時子程序的流程圖如下圖39所示。開始初始化，R2=6是否有信號輸入Y存入寄存器A返回NR21=0？Y報(bào)錯N圖38 子程序1的流程圖 圖39 延時子程序流程圖第4章 結(jié)論與發(fā)展前景 結(jié)論本次設(shè)計(jì)題目是電動車無刷電機(jī)控制器的相序檢測系統(tǒng)，由于我所設(shè)計(jì)的電路是在理想條件下的電路，而且所選元件以及元件參數(shù)都是在理想狀態(tài)下進(jìn)行選擇的,所以設(shè)計(jì)的最終結(jié)果可能在實(shí)際電路上會出現(xiàn)一定的偏差。由于時間的原因沒有能夠做出實(shí)際的電路板，也就無法進(jìn)行調(diào)試，然而從理論上分析可以達(dá)到以下的預(yù)期要求：(1)通過數(shù)碼管顯示可以確定電機(jī)控制器的好壞。(2)可以通過數(shù)碼管讀出電機(jī)的角度。(3)霍耳相序?qū)⒁来纬尸F(xiàn)在相應(yīng)的數(shù)碼管上。(4)無刷電機(jī)控制器的相序依次呈現(xiàn)在數(shù)碼管上。 前景展望目前，電動車所占的市場份額越來越大，并有取代傳統(tǒng)自行車的趨勢。而且隨著微機(jī)控制技術(shù)的飛速發(fā)展，現(xiàn)在已經(jīng)開始出現(xiàn)了電動車智能控制檢測系統(tǒng)，并且這項(xiàng)技術(shù)已經(jīng)走向了市場，被廣大的維修技術(shù)人員所接受。但是現(xiàn)在在市場上的應(yīng)用只是處于萌芽狀態(tài)，還沒有發(fā)展起來，大多數(shù)電動車維修技術(shù)人員仍偏向于用硬件電路檢測電動車系統(tǒng)。但是隨著市場對電動車需求的擴(kuò)大，維修人員選用智能檢測系統(tǒng)將是必要的發(fā)展方向。參考文獻(xiàn)[1] 潘建. 無刷直流電機(jī)控制器MC33035的原理及應(yīng)用[J]. 國外電子元器件. 2003,(8): 38～41[2] 周志敏,紀(jì)愛華. 電動自行車使用與維修技術(shù)問答[M].北京：人民郵電出版社,2006.[3] 王萍,王正茂,姚剛,[J]. 微電機(jī). 2003,(6):16～18[4] 謝炎民,劉孝偉. 電動自行車維修速成[M]. 福建：福建科學(xué)技術(shù)出版社,2006.[5] 張?zhí)煨?張慧玲. 電動自行車電器原理與維修[M]. 成都：電子科技大學(xué),2003.[6] [M].北京:國防工業(yè)出版社,2006.[7] [M]. 北京：北京航空航天大學(xué)出版社,2002.[8] 王港元,方安安. 電子技能基礎(chǔ)[M]. 四川：四川大學(xué)出版社，2001. [9] 樓然苗,李光飛. 51系列單片機(jī)設(shè)計(jì)實(shí)例[M]. 北京：北京航空航天大學(xué)出版社,2006.[10] 集成電路手冊編委會. 標(biāo)準(zhǔn)集成電路手冊CMOS 4000系列電路[M]. 北京：電子工業(yè)出版社,1995.[11] 龐勇,賀益康,方衛(wèi)中. 基于專用控制芯片的永磁無刷直流電機(jī)控制器[J]. 微電機(jī),1999， 32(3)：15～17[12] 童詩白,. 北京：高等教育出版社,2001.[13] 李若昕,焦小澄．電動自行車控制器測試儀的設(shè)計(jì)與實(shí)現(xiàn)[J]. 電子工程師測控技術(shù)與設(shè) ,(5)：16～18[14] MC33033 W Semiconductor Components .[15] MC33035 W Semiconductor Components Industries. .[16] 99輔助分析與設(shè)計(jì)+ 5V直流穩(wěn)壓電源[J]. 沙洲職業(yè)工學(xué)院學(xué)報(bào). 2003，6(1)：10～13致 謝經(jīng)過一學(xué)期以來的努力，《無刷電機(jī)控制器的相序檢測系統(tǒng)設(shè)計(jì)》課題取得了階段性的成績，論文已經(jīng)完成。本課題是在鄧曉燕老師的悉心指導(dǎo)下完成的，從課題的選擇到論文的最終完成，鄧?yán)蠋熥允贾两K給予我精心的指導(dǎo)和親切的關(guān)懷，為論文的順利完成傾注了大量的心血。鄧?yán)蠋焽?yán)謹(jǐn)?shù)闹螌W(xué)作風(fēng)和兢兢業(yè)業(yè)的科研精神以及真誠的待人態(tài)度給了我深刻的影響，使我受益非淺。感謝鄧?yán)蠋熢谡n題開展中對我的鼓勵和信任，這使我在實(shí)踐中增長了見識，不僅學(xué)到很多知識，更學(xué)到做人的道理。他處處為學(xué)生著想的寬容胸懷使我滿懷感激。值此論文完成之際，謹(jǐn)向鄧?yán)蠋煴磉_(dá)我的敬意和感謝！在課題研究設(shè)計(jì)的整個過程中，石家莊鐵道學(xué)院實(shí)驗(yàn)室的老師們也給予了充分的幫助和配合，使我們能如期的完成各項(xiàng)任務(wù)。在此對實(shí)驗(yàn)室的劉利賢老師、陳立松老師、馮濤老師和胡曉娟老師表示衷心的感謝。值得我永遠(yuǎn)銘記的是，我的朋友和同學(xué)們也對我?guī)椭芏啵刮腋禹樌耐瓿僧厴I(yè)設(shè)計(jì)，在此，我謹(jǐn)表示深深的感謝。附 錄附錄A 外文資料翻譯英文資料CY7C68013EZUSB174。 FX2? USB MicrocontrollerHighSpeed USB Peripheral ControllerEZUSB174。 FX2? FeaturesCypress’s EZUSB174。 FX2? is the world’s first USB integrated microcontroller. By integrating the USB transceiver, SIE,enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very costeffective solution that provides superior timetomarket advantages. The ingenious architecture of FX2 results in data transfer rates of 56 Mbytes per second, the maximum allowable USB bandwidth, while still using a lowcost 8051 microcontroller in a package as small as a 56 SSOP. Because it incorporates the USB transceiver, the FX2 is more economical, providing a smaller footprint solution than USB SIE or external transceiver implementations. With EZUSB FX2, the Cypress Smart SIE handles most of the USB and protocol in hardware, freeing the embedded microcontroller for applicationspecific functions and decreasing development time to ensure USB patibility. The General Programmable Interface (GPIF) and Master/Slave Endpoint FIFO (8 or 16bit data bus) provides an easy and clueless interface to popular interfaces such as ATA, UTOPIA, EPP, PCMCIA, and most DSP/processors.Functional Overview USB Signaling SpeedFX2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision , dated April 27, 2000:? Full speed, with a signaling bit rate of 12 Mbps? High speed, with a signaling bit rate of 480 MbpsFX2 does not support the lowspeed signaling mode of Mbps. 8051 MicroprocessorThe 8051 microprocessor embedded in the FX2 family has 256 bytes of register RAM, an expanded interrupt system, three timer/counters, and two USARTs. 8051 Clock FrequencyFX2 has an onchip oscillator circuit that uses an external 24MHz (177。100 ppm) crystal with the following characteristics:? Parallel resonant? Fundamental mode? 500 μW drive level? 27–33 pF (5% tolerance) load capacitors.An onchip PLL multiplies the 24MHz oscillator up to 480 MHz, as required by the transceiver/PHY, and internal counters divideit down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed by the 8051 through the CPUCS register, dynamically.The CLKOUT pin, which can be threestated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, atthe selected 8051 clock frequency—48, 24, or 12 MHz. USARTSFX2 contains two standard 8051 USARTs, addressed via Special Function Register (SFR) bits. The USART interface pins areavailable on separate I/O pins, and are not multiplexed with port pins. UART0 and UART1 can operate using an internal clock at 230 KBaud with no more than 1% baud rate error. 230KBaud operation is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. The internal clock adjusts for the 8051 clock rate (48, 24, 12 MHz) such that it always presents the correct frequency for 230KBaud operation. Note. 115KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1, respectively. Special Function Registers (SFR)Certain 8051 SFR addresses are populated to provide fast access to critical FX2 functions. These SFR additions are shown in Table 31. Bold type indicates nonstandard, enhanced 8051 registers. The two SFR rows that end with “0” and “8” contain bitaddressable registers. The four I/O ports A–D use the SFR addresses used in the standard 8051 for ports 0–3, which are not implemented in FX2. Because of the faster and more efficient SFR addressing, the FX2 I/O ports are not addressable in external RAM space (using the MOVX instruction). I2Cpatible BusFX2 supports the I2Cpatible bus as a master only at 100/400 kbps. SCL and SDA pins have opendrain outputs and hysteresis inputs. These signals must be pulled up to , even if no I2C patibl