ict測試原理及程式簡介(編輯修改稿)
2025-05-26 04:57 本頁面
【文章內(nèi)容簡介】 0K DVM S Node E has no current flow. It is capacitively isolated and cannot be tested in Pins Test. Pins Test Syntax nodes A nodes B nodes C nodes D !nodes E” ! node capacitively isolated nodes ”F nodes ”G Pins Test Called from testplan Pins test的預(yù)定義 sub Set_Custom_Option …… global Off, Pretest, Failure ！設(shè)置全局常量 global Chek_Point_Mode …… Chek_Point_Mode=Pretest !choose {Off, Pretest, Failure} ！選擇 pins測試模式， off＝不進(jìn)行 pins測試 ！ pretest＝在其它測試前進(jìn)行 pins測試 ！ failure＝其它測試 fail后，進(jìn)行 pins測試 end sub Pins測試的調(diào)試 ① Pins測試中的節(jié)點(diǎn)排列順序不影響測試結(jié)果 ② Pins測試中沒有其他測試選項 ? 所以 pins測試只有 node的取舍 哪些節(jié)點(diǎn) pins不可測 ? ? 電容阻隔的點(diǎn)（ capacitively isolated）－ IPG自動注釋 ? 只連到 IC的 NC腳的 － IPG自動注釋 ? 所連器件在板上都沒有放 (no pop)的 － 手動確認(rèn) Part 4 ? Shorts Test amp。 Opens Test L201 L2011 L2012 100 ohms DVM Shorts Test overview Shorts Test ! IPG: rev date threshold 12 settling delay settling delay short “L2011” to “L2012” settling delay short “J2011” to “J2012” . . . threshold 1000 . . . nodes “Data7” nodes “R2012” nodes “R2011” . . . threshold 8 . . . nodes “R2022” nodes “R2021” nodes “GND” DVM L201 Series Resistance = 6ohms R202 at 33ohms DVM R201 at 20k L2011 L2012 R2011 R2012 R2021 R2022 Expected Shorts L201 L2011 L2012 100 ohms DVM 如圖，對 L201 進(jìn)行 shorts測試，預(yù)期為短路。 a).設(shè)置閥值為 12歐姆，如果 R測量12(threshold) ， 則測試 pass，反之， fail。 b).設(shè)置從加信號到開始測量的延時，以致等待信號穩(wěn)定。 c).測量兩個節(jié)點(diǎn)之間的阻值，并判斷！ 語法如下： !@ In the “shorts” file @! !@ Syntax @! !@ short “Node_1” to “Node_2” @! threshold 12 Settling delay 50u Settling delay 525u Shorts “L2011” to “L2012 Shorts Test (Good Board) Testing For Shorts 100mV 100 W “ A” “ B” “ C” “ D” “ E” “ F” “ G” “ Node_Names” Shorts Test (Bad Board) Testing For Shorts 100mV 100 W “ A” “ B” “ C” “ D” “ E” “ F” “ G” ? Which node is shorted to node C? A short has been detected from node C to one of the remaining nodes D, E, F or G Short
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