【文章內(nèi)容簡介】 esults in a less reliable design. A mon technique to remove gated clock is to make use of the clock enable pin of the flipflop. For example, if you have a signal clko = clki amp。 a amp。 b driving the clock pin of a flipflop, you can eliminate the gated clock by feeding clki directly to the FF clock pin, and have another signal en = a amp。 b connected to the clock enable pin of the FF. ( 參考譯文：在現(xiàn)代高速數(shù)字設(shè)計當(dāng)中 , 不建議使用組合邏輯門控時鐘信號 , 因為這將會在選通的時鐘信號上產(chǎn)生短時脈沖波形干擾 , 導(dǎo)致錯誤觸發(fā) flipflop. 這是缺乏可靠性的設(shè)計 . 移除門控時鐘通常所采用的技巧是使用 flipflop 的時鐘使能引腳 . 例如 , 如果有一個信號 clko = clki amp。 a amp。 b 正在驅(qū)動 flipflop的時鐘引腳 , 則可以通過直接將clki傳遞給 FF 時鐘引腳 , 并將另一個信號 en = a amp。 b 與 FF的時鐘使能引腳連接 , 來消除門控時鐘 . ) By removing the gated clock, you no longer have the problem of clock delay. Also the design is more robust. (移除門控時鐘后 , 就不再有時鐘延遲的問題了 . 而且這種設(shè)計也比較可靠 . ) 30． FPGA生產(chǎn)產(chǎn)商提供了 IP, 如何用第三方軟件 , 如 Advantage 或 ACTIVE vhdl, 調(diào)用并進行仿真？ 答： The IPs provided by Xilinx, e. g. PCI, e with simulation models which can be processed by 3rd part simulation tools like Modelsim. So there is no problem for functional simulation. Timing simulation can be done by exporting the postlayout vhdl/verilog model from Xilinx ISE software. In some cases, sample testbenches are also included. （參考譯文： Xilinx提供的 IP, 例如 PCI, 是與仿真模型一同提供的 , 這種模型可由第三方仿真工具 , 如Modelsim 來處理 . 因此對功能仿真來說 , 沒有問題 . 通過從 Xilinx ISE 軟件中導(dǎo)出postlayout vhdl/verilog可以執(zhí)行定時仿真 . 在某些情況下 , 也包括樣本測試平臺 . ） 31． “ As a good design practice, never use gate delay to implement your delay logic under all circumstances” . Please tell me what does gate delay(閘 ) mean?（“一個好的設(shè)計 , 在所有情況下都決不會使用門延遲來實現(xiàn)延遲邏輯 . ”此處“門延遲”是什么意思？） 答： “ By gate delay I mean using a series of logic gates to introduce certain amount of delay in the design. This is highly undesirable since gate delay changes with factors like temperature and process technology. The design may fail as temperature changes or using a different version silicon. Also designs relying on gate delay are not portable, meaning that you need to redesign the whole circuit whenever you want to change to another product series or part number, simply because the gate delay changes as well. （參考譯文：“門延遲”指得是使用一系列邏輯門將一定數(shù)量的延遲導(dǎo)入到設(shè)計中 . 既然門延遲更改像溫度和處理技術(shù)這樣的因素 , 所以 , 這是很不合適的 . 由于溫度的改變或使用不同版本的芯片 , 設(shè)計可能會失敗 . 依賴門延遲的設(shè)計也不是可移植的 , 也就是說 , 要更改另一產(chǎn)品系列或部件號時 , 需要重新設(shè)計整個電路 , 只因為更改了門延遲 . ） Always use fully synchronous design. You never need to reply on gate delay if your design is fully synchronous. （始終使用完全同步設(shè)計 . 如果設(shè)計是全同步的 , 則無需回應(yīng)門延遲 . ） 32． This time I download another program to another chip SpartanII XC2S50PQ208 in another circuit, while it fails, and show the following message: . . . Checking boundaryscan chain integrity. . . ERROR:JTag Boundaryscan chain test failed at bit position 39。339。 on instance 39。***39。(a substitute for the real name of file). A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage. ERROR:JTag Boundary scan chain has been improperly specified. Please check your configuration and reenter the boundaryscan chain information. Boundaryscan chain validated unsuccessfully. ERROR:JTag : The boundaryscan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this mand. With so many messages, I don39。t know what to do! I try many times but only fail, and doubt whether there is something wrong with the circuit?But the powers checked in circuit are right. Would you please give me some advice to crack the problem?（有一次 , 將程序下載至 SpartanII XC2S50PQ208 芯片電路 , 結(jié)果發(fā)生了故障 , 并顯示以下消息：“ . . . Checking boundaryscan chain integrity. . . ERROR:JTag Boundaryscan chain test failed at bit position 39。339。 on instance 39。***39。(實際的文件名 )” . 問題可能在硬件配置 . 檢查了連線、掃描鏈路和電源接頭都沒有問題 . 特定的掃描鏈路配置與實際的硬件相 匹配 , 電源充足且 電壓正常 . “ ERROR:JTag Boundary scan chain has been improperly specified. Please check your configuration and reenter the boundaryscan chain information. Boundaryscan chain validated unsuccessfully. ERROR:JTag : The boundaryscan chain has not been declared correctly. Verify the syntax and correctness of the device BSDL files, correct the files, reset the cable and retry this mand. ”這么多出錯消息 , 什么原因 , 怎么辦？） 答： Usually it is the result of a broken JTAG chain or noisy chain. Most monly, the cable is not connected properly, a trace is not correct on the board, other devices in the chain are causing a problem, or a noisy parallel port exists. Try using a different PC. You can also add a 4. 7K pullup on the PROG pin of the FPGA and see if it helps. （通常 , 這是由于中斷的 JTAG鏈或噪聲鏈 . 最常見的原因是 , 連線不正確 , 板子上的跡線不正確 , 鏈路中的其它器件導(dǎo)致問題 , 或者存在噪聲并口 . 試一下使用不同的 PC. 也可以在 FPGA的 PROG引腳上增加一個4. 7K 的上拉電阻 , 看看是否有幫助 . ） 33． 在 VHDL 中 , 定義為 SIGNAL 的量起到什么作用？什么時候需要定義這個量？下面的程序 ARCHITECTURE EXER2_ARCH OF EXERCISE2 IS SIGNAL TEM: STD_LOGIC。 BEGIN TEM=PIN50 AND PIN51。 PIN8 =TEM。 END EXER2_ARCH。 和如下的程序有何區(qū)別？ ARCHITECTURE EXER2_ARCH OF EXERCISE2 IS BEGIN PIN8=PIN50 AND PIN51。 END EXER2_ARCH。 答： If PIN8 is declared in your port list, the 2 examples are identical. From a hardware design39。s perspective, you can think of a vhdl signal as an electrical signal. So basically you can declare every object as signal. From a simulation39。s perspective, there is a fundamental difference between signal and variable in vhdl. A variable is nothing more than an object that holds a value. A variable assignment occurs instantly in a vhdl simulation. Also, a variable can only exist within a process, so it cannot transfer values across processes. A signal, on the other hand, has a history of values. Whenever a signal