【正文】 摘 要 本設(shè)計(jì)為一個(gè)多功能的數(shù)字時(shí)鐘，具有時(shí)、分、秒計(jì)數(shù)顯示功能，以 24 小時(shí)循環(huán)計(jì)數(shù)；具有校對(duì)功能。 本設(shè)計(jì)采用 EDA 技術(shù)，以硬件描述語言 Verilog HDL 為系統(tǒng)邏輯描述語言設(shè)計(jì)文件，在 QUARTUSII 工具軟件環(huán)境下，采用自頂向下的設(shè)計(jì)方法，由各個(gè)基本模塊共同構(gòu)建了一個(gè)基于 FPGA 的數(shù)字鐘。 系統(tǒng)由時(shí)鐘模塊、控制模塊、計(jì)時(shí)模塊、數(shù)據(jù)譯碼模塊、顯示以及組成。經(jīng)編譯和仿真所設(shè)計(jì)的程序，在可編程邏輯器件上下載驗(yàn)證，本系統(tǒng)能夠完成時(shí)、分、秒的分別顯示，按鍵進(jìn)行校準(zhǔn)，整點(diǎn)報(bào)時(shí)，鬧鐘功能。 關(guān)鍵詞 ： 數(shù)字時(shí)鐘，硬件描述語言， Verilog HDL， FPGA Abstract The design for a multifunctional digital clock, with hours, minutes and seconds count display to a 24hour cycle count。 have proof functions function. The use of EDA design technology, hardwaredescription language VHDL description logic means for the system design documents, in QUAETUSII tools environment, a topdown design, by the various modules together build a FPGAbased digital clock. The main system make up of the clock module, control module, time module, data decoding module, display and broadcast module. After piling the design and simulation procedures, the programmable logic device to download verification, the system can plete the hours, minutes and seconds respectively, using keys to cleared , to calibrating time. And on time alarm and clock for digital clock. Keywords： digital clock,hardware description language,Verilog HDL,FPGA I 目 錄 摘 要 .....................................................................................................................................................................1 Abstract ....................................................................................................................................................................2 第一章 緒論 ...............................................................................................................................................1 . 選題意義與研究現(xiàn)狀 .................................................................................... 1 . 國(guó)內(nèi)外研究及趨 勢(shì) ........................................................................................ 1 . 論文結(jié)構(gòu) ........................................................................................................ 2 第二章 編程軟件及語言介紹 ..................................................................................................................3 Quarters II 編程環(huán)境介紹 .............................................................................. 3 菜單欄 ..................................................................................................................................3 工具欄 ..................................................................................................................................8 功能仿真流程 .....................................................................................................................9 Verilog HDL 語言介 .................................................................................... 10 什么是 verilog HDL 語言 ............................................................................................... 10 主要功能 ........................................................................................................................... 11 第三章 數(shù)字化時(shí)鐘系統(tǒng)硬件設(shè)計(jì) ...................................................................................................... 13 系統(tǒng)核心板電路分析 .................................................................................. 13 系統(tǒng)主板電路分析 ...................................................................................... 15 時(shí)鐘模塊電路 .................................................................................................................. 15 顯示電路 ........................................................................................................................... 15 鍵盤控制電路 .................................................................................................................. 17 蜂鳴電路設(shè)計(jì) .................................................................................................................. 17 第四章 數(shù)字化時(shí)鐘系統(tǒng)軟件設(shè)計(jì) ...................................................................................................... 18 整體方案介紹 .............................................................................................. 18 整體設(shè)計(jì)描述 .................................................................................................................. 18 整體信號(hào)定義 .................................................................................................................. 19 模塊框圖 ........................................................................................................................... 20 分頻模塊實(shí)現(xiàn) .............................................................................................. 20 分頻模塊描述 .................................................................................................................. 20 II 分頻模塊設(shè)計(jì) .................................................................................................................. 20 分頻模塊仿真 .................................................................................................................. 21 計(jì)時(shí)模塊實(shí)現(xiàn) .............................................................................................. 21 計(jì)時(shí)模塊描述與實(shí)現(xiàn) .................................................................................. 21 計(jì)時(shí)模塊仿真 .............................................................................................. 23 按鍵處理模塊實(shí)現(xiàn) ...................................................................................... 23 按鍵處理模塊描述 .......................................................................................................... 23 按鍵去抖處理模塊設(shè)計(jì) .................................................................................................. 24 按鍵模塊去抖仿真 .......................................................................................................... 24 鬧鐘模塊實(shí)現(xiàn) .............................................................................................. 25 鬧鐘模塊設(shè)計(jì) ...................................................