【正文】 nter design, using Ver ilog H DL language designed a synchronous presettable down counter, the counter can be implemented according to the control signals are counted Addition and subtraction counting from a given the preset starts counting, and gives detailed VerilogHDL source code. Finally, the design of the incentive code its simulation, experimental results show that the design meets the functional requirements, you can achieve the intended function. Key words: Decimal counter。 Quartus Ⅱ 。通信 102班，姓名 青瓜 基于 FPGA的計數(shù)器 設(shè)計 III 目 錄 摘 要 .........................................................................................................................................I Abstract ..................................................................................................................................... II 第 1 章 緒論 ............................................................................................................................ 1 計數(shù)器的種類 ................................................................................................................ 1 計數(shù)器的發(fā)展 ................................................................................................................ 1 第 2 章 設(shè)計環(huán)境 .................................................................................................................... 2 Quartus II .................................................................................................................... 2 軟件簡介 ............................................................................................................ 2 功能 .................................................................................................................... 3 Verilog HDL 硬件描述語言 ....................................................................................... 4 語言簡介 ............................................................................................................ 4 主要能力 ............................................................................................................ 4 語言用途 ............................................................................................................ 6 Verilog HDL 的發(fā)展歷史 .................................................................................. 6 主要應(yīng)用 .............................................................................................................. 7 Electronic Design Automation .................................................................................... 8 第 3 章 設(shè)計思路 .................................................................................................................. 10 輸入 模塊 .................................................................................................................. 10 寄存器 模塊 ............................................................................................................... 11 輸出 模塊 ................................................................................................................... 11 計數(shù) 模塊 ................................................................................................................... 11 第 4 章 程序設(shè)計 .................................................................................................................. 13 主程序 ....................................................................................................................... 13 always 語句 ............................