【正文】 els below the amplitude at the operating frequency of the oscillator using a 1Hz bandwidth) at two or more frequency displacements from the operating frequency of the oscillator. This measurement has particular application to performance in the analog munications industry.Do DDS devices have good phase noise?Figure 9. Typical output phase noise plotfor the AD9834. Output frequency is 2MHz and M clock is 50 MHz.Noise in a sampled system depends on many factors. Referenceclock jitter can be seen as phase noise on the fundamental signal in a DDS system。 it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overflows and pletes its equivalent of a sinewave cycle. The number of discrete phase points contained in the wheel is determined by the resolution of the phase accumulator (n), which determines the tuning resolution of the DDS. For an n = 28bit phase accumulator, an M value of 0000...0001 would result in the phase accumulator overflowing after 28 referenceclock cycles (increments). If the M value is changed to 0111...1111, the phase accumulator will overflow after only 2 referenceclock cycles (the minimum required by Nyquist). This relationship is found in the basic tuning equation for DDS architecture:where: fOUT = output frequency of the DDS M = binary tuning word fC = internal reference clock frequency (system clock) n = length of the phase accumulator, in bits Changes to the value of M result in immediate and phasecontinuous changes in the output frequency. No loop settling time is incurred as in the case of a phaselocked loop. As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting filtering on the output. When generating a constant frequency, the output of the phase accumulator increases linearly, so the analog waveform it generates is inherently a ramp. Then how is that linear output translated into a sine wave? Figure 5. Signal flow through the DDS architecture.A phase to amplitude lookup table is used to convert the phaseaccumulator’s instantaneous output value (28 bits for AD9833)—with unneeded lesssignificant bits eliminated by truncation—into the sinewave amplitude information that is presented to the (10 bit) D/A converter. The DDS architecture exploits the symmetrical nature of a sine wave and utilizes mapping logic to synthesize a plete sine wave from onequartercycle of data from the phase accumulator. The phaseto amplitude lookup table generates the remaining data by reading forward then back through the lookup table. This is shown pictorially in Figure 5.What are popular uses for DDS? Applications currently using DDSbased waveform generation fall into two principal categories: Designers of munications systems requiring agile (., immediately responding) frequency sources with excellent phase noise and low spurious performance often choose DDS for its bination of spectral performance and frequencytuning resolution. Such applications include using a DDS for modulation, as a reference for a PLL to enhance overall frequency tunability, as a local oscillator (LO), or even for direct RF transmission. Alternatively, many industrial and biomedical applications use a DDS as a programmable waveform generator. Because a DDS is digitally programmable, the phase and frequency of a waveform can be easily adjusted without the need to change the external ponents that would normally need to be changed when using traditional analogprogrammed waveform generators. DDS permits simple adjustments of frequency in real time to locate resonant frequencies or pensate for temperature drift. Suchapplications include using a DDS in adjustable frequency sources to measure impedance (for example in an impedancebased sensor), to generate pulsewave modulated signals for microactuation, or to examine attenuation in LANs or telephone cables. What do you consider to be the key advantages of DDS to designers of realworld equipment and systems? Today’s cost petitive, high performance, functionally integrated DDS ICs are being mon in both munication systems and sensor applications. The advantages that make them attractive to design engineers include: ? digitally controlled microhertz frequencytuning and subdegree phasetuning capability, ? extremely fast hopping speed in tuning output frequency (or phase)。每一個技術(shù)說明附評估電路板原理圖包含的信息，并顯示最佳推薦電路板設(shè)計和布局的做法。圖12如何評價你的DDS器件？所有DDS器件具有一個評價板可供購買。以圖12為例，MCLK的是設(shè)置為25MHz和所需的輸出頻率設(shè)置為10MHz。這些工具將如何幫助我的DDS方案？所有這一切需要的是必要的頻率輸出和系統(tǒng)的參考時鐘頻率。一個例子是如圖11所示。你有更容易進行編程和DDS的性能預(yù)測的工具嗎？在線互動設(shè)計工具是一個選拔調(diào)整，給定一個時鐘和期望輸出頻率和階段。由于頻率明智的選擇，有在25MHz的窗口沒有諧波頻率，至少有80dB以下的信號（SFDR=80dB）。(a) (b)圖10 控制時鐘為50MHz的AD9834輸出圖11 由互動設(shè)計工具提供屏幕上陳述輸出時鐘為50的典型情節(jié)取自AD9834是在圖10所示。SFDR是一個重要的規(guī)范和應(yīng)用渠道的應(yīng)用程序，通信頻譜的頻率與其他被共享。無雜散動態(tài)范圍（SFDR）是指信號和水平最高的比率（衡量分貝之間）的最高級別，在頻譜信號包括相關(guān)的諧波頻率分量。隨著頻率的劃分，相同數(shù)量的抖動一段較長的時間內(nèi)發(fā)生，減少其對系統(tǒng)時間的百分比。由于每個時鐘將已經(jīng)有一定抖動，選擇一個低抖動振蕩器是至關(guān)重要的開始。即使是一個簡單的放大器，逆變器，或?qū)⒂兄诰彌_抖動信號。高品質(zhì)，低相位噪聲晶體振蕩器將抖動小于35皮秒（ps）的時期，積累了許多以百萬計的由熱噪聲引起的抖動時鐘邊緣，不穩(wěn)定的電子振蕩器，外部干擾通過電源，甚至輸出連接。振蕩器將有一個完美的上升和下降沿時間正是經(jīng)常在瞬間發(fā)生的，絕不會有所不同。圖9顯示了相位噪聲DDS在這種情況下一個典型情節(jié)，設(shè)備的AD9834。該DAC還有助于在系統(tǒng)中的噪音。圖。對于一個完全可以由一個二進制編碼表示的比例，也沒有截斷誤差。DDS器件具有良好的相位噪音？對采樣系統(tǒng)的噪聲，取決于很多因素。它是衡量作為單邊帶從頻率變化造成的噪音低于在使用振蕩器的（工作頻率為1Hz）的帶寬在兩個或多個頻率位移振蕩器工作頻率振幅分貝。什么是基于DDS系統(tǒng)的主要性能規(guī)格？相位噪聲，抖動，無雜散動態(tài)范圍（SFDR）。AD9833和AD9834的有12位分辨率的階段。這將設(shè)置DDS輸出到一個已知的階段，它作為共同的參照點，允許符合多個DDS的同步裝置。使用這種設(shè)置，有可能做智商調(diào)制。多個DDS器件可以同步嗎，也就是說，智商能力？圖8 多個DDS同步模式它可以使在同一主機兩個單DDS器件的時鐘運行輸出的兩個信號的相位關(guān)系可直接控制。在fourphase調(diào)制（正交PSK或QPSK調(diào)制），可能相角為0，+90，90，和180度，每相移可以代表兩個信號分子。更多復(fù)雜的PSK形式選用4或8波階段。改變這種調(diào)制的載波相位，因此產(chǎn)生的PS