【正文】 (AGU) based on this high performance video development and verification platform. The way of software and afterimplementation verification processes of the AGU is also introduced. Finally, parisons of synthesis with the same constrain are given among the MPEG4 codec development system, high performance video development and verification platform and SMIC m cell library. Keywords： Video codec, Development and verification platform, High performance 浙江大學(xué)碩士學(xué)位論文 目 錄 摘 要 ............................................................................................................................. 1 ABSTRACT ..................................................................................................................... 3 目 錄 ............................................................................................................................. 4 圖表目錄 .......................................................................................................................... 6 第 1 章 緒 論 ................................................................................................................. 8 視頻編碼標(biāo)準(zhǔn)的發(fā)展 ............................................................................................ 8 視頻編解碼芯片開發(fā) ............................................................................................ 9 視頻編解碼芯片開發(fā)方法 ......................................................................... 10 ASIC設(shè)計(jì)流程 ......................................................................................... 10 FPGA與 ASIC設(shè)計(jì) .....................................................................................11 視頻編解碼器體系結(jié)構(gòu) ............................................................................. 12 本研究的意義及論文主要內(nèi)容 ........................................................................... 14 第 2 章 MPEG4編解碼芯片開發(fā)系統(tǒng) ............................................................................ 15 MPEG4編解碼芯片開發(fā)系統(tǒng)簡介 ..................................................................... 15 性能指標(biāo) ................................................................................................. 15 框架結(jié)構(gòu) ................................................................................................. 15 重要硬件模塊設(shè)計(jì) ................................................................................... 17 MPEG4專用結(jié)構(gòu)視頻解碼芯片開發(fā) .................................................................. 19 MPEG4專用結(jié)構(gòu)解碼芯片系統(tǒng)結(jié)構(gòu) ........................................................ 19 系統(tǒng)子模塊設(shè)計(jì) ...................................................................................... 20 MPEG4專用結(jié)構(gòu)視頻解碼芯片 ............................................................... 21 MPEG4專用解碼芯片驗(yàn)證系統(tǒng) ......................................................................... 22 MPEG4編解碼芯片開發(fā)系統(tǒng)的缺陷與不足 ....................................................... 24 本章小節(jié) .......................................................................................................... 25 第 3 章 高性能視頻開發(fā)驗(yàn)證平臺設(shè)計(jì) ............................................................................ 26 平臺簡介 .......................................................................................................... 26 設(shè) 計(jì)目標(biāo)與應(yīng)用范圍 ............................................................................... 26 框架結(jié)構(gòu) ................................................................................................. 26 平臺優(yōu)勢 ................................................................................................. 28 平臺硬件系統(tǒng)設(shè)計(jì) ............................................................................................ 29 母板 ........................................................................................................ 29 母板整體結(jié)構(gòu) ................................................................................. 29 FPGA........................................................................................... 31 DDR400 外存儲器接口 ............................................................... 32 SRAM/SDRAM 外存儲器接口 ..................................................... 33 電源解決方案 ................................................................................. 34 輸入輸出與測試端口 ....................................................................... 38 子板 ........................................................................................................ 39 子板整體結(jié)構(gòu) ................................................................................. 39 浙江大學(xué)碩士學(xué)位論文 ........................................................................................... 42 視頻輸入 ........................................................................................ 42 平臺高速 PCB 設(shè)計(jì)要點(diǎn) .................................................................................... 43 PCB阻抗控制 .......................................................................................... 43 DDR400接口雙向拓?fù)浣Y(jié)構(gòu)與終端 ............................................................ 44 平臺應(yīng)用軟件和接口應(yīng)用模塊 ........................................................................... 45 開發(fā)應(yīng)用軟件 .......................................................................................... 45 接口應(yīng)用模塊 .......................................................................................... 46 USB接口應(yīng)用模塊 ......................................................................... 46 RS232 接口應(yīng)用模塊 ....................................................................... 47 視頻輸出接口應(yīng)用模塊 ................................................................... 48 SDRAM 接口應(yīng)用模塊 .................................................................... 49 SRAM 接口應(yīng)用模塊 ...................................................................... 52 DDR400接口應(yīng)用模塊 .................................................................. 52 FPGA接口連接 ...........................