【正文】 Td1,tempy0,tempy1,date0,date1)。elsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0101” and mon1=“0000”)or(mon0=“0111” and mon1=“0000”)or(mon0=“1000” and mon1=“0000”)or(mon0=“0000” and mon1=“0001”)or(mon0=“0010”and mon1=“0001”))thenoddmonth_sub_day(Td0,Td1,date0,date1)。else evenmonth_sub_day(Td0,Td1,date0,date1)。end if。end if。end if。end if。end process u2。u3:process(ce)beginif rising_edge(clk)thenif(lock/=“000” and lock/=“001”)thenovelsif(ce=39。139。)thenif(mon0=“0010” and mon1=“0000”)thenif((tempy1=39。039。 and tempy0=“00”)or(tempy1=39。139。 and tempy0=“10”))thenif(date0=“1001” and date1=“0010”)thenovelse ovend if。elsif(date0=“1000” and date1=“0010”)then ovelsif((mon0=“0001” and mon1=“0000”)or(mon0=“0011” and mon1=“0000”)or(mon0=“0010” and mon1=“0000”)or(mon0=“0111” and mon1=“0000”)or(mon0=“1000” or(mon0=“0000” and mon1=“0001”)or(mon0=“0010” and mon1=“0001”))thenif(date0=“0001” and date1=“0011”)thenovelse ovend if。elsif(date0=“0000” and date1=“0011”)thenovelse ovend if。end if。end if。end process u3。end Behavioral。library IEEE。use 。andmon1=“0000”)use 。use 。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。use 。use 。entity h_m_s_time isPort(clk0,clk1,ce : in std_logic。sec0,sec1 : buffer std_logic_vector(3 downto 0)。lock : in std_logic_vector(2 downto 0)。up : in std_logic。min0,min1 : buffer std_logic_vector(3 downto 0)。hour0,hour1 : buffer std_logic_vector(3 downto 0)。ov : out std_logic)。end h_m_s_time。architecture Behavioral of h_m_s_time is signal Ts0,Ts1,Tm0,Tm1,Th0,Th1:std_logic_vector(3 downto 0)。signal clk:std_logic。beginTs0beginif(lock=“000” or lock=“001”)thenclkelse clkend if。end process u1。u2: process(clk,lock)beginif rising_edge(clk)thenif(ce=39。139。)thenif(lock=“000”)or(lock=“001”)or(lock=“111” and up=39。139。)thenaddsec_addmin(Ts0,Ts1,sec0,sec1)。end if。if(lock=“111” and up=39。039。)thensubsec_submin(Ts0,Ts1,sec0,sec1)。end if。if(lock=“000” or lock=“001”)thenif(sec0=“1001” and sec1=“0101”)thenaddsec_addmin(Tm0,Tm1,min0,min1)。end if。if(sec0=“1001” and sec1=“0101” and min0=“1001” and min1=“0101”)thenaddhour(Th0,Th1,hour0,hour1)。end if。if(sec0=“1001” and sec1=“0101” and min0=“1001” and min1=“0101”and hour0=“0011” and hour1=“0010”)thenovelse ovend if。end if。if(lock=“110” and up=39。139。)thenaddsec_addmin(Tm0,Tm1,min0,min1)。end if。if(lock=“101” and up=39。039。)thensubsec_submin(Tm0,Tm1,min0,min1)。end if。if(lock=“101” and up=39。139。)thenaddhour(Th0,Th1,hour0,hour1)。end if。if(lock=“101” and up=39。039。)thensubhour(Th0,Th1,hour0,hour1)。end if。end if。end if。end process u2。end Behavioral。library IEEE。use 。use 。use 。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。use 。entity LED_disp isPort(lock : in std_logic_vector(2 downto 0)。sec0,sec1,min0,min1,hour0,hour1 : in std_logic_vector(3 downto 0)。date0,date1,mon0,mon1,year0,year1 : in std_logic_vector(3 downto 0)。a0,a1,b0,b1,c0,c1 : out std_logic_vector(3 downto 0))。end LED_disp。architecture Behavioral of LED_disp is begin process(lock,sec0,sec1,min0,min1,hour0,hour1,date0,date1,mon0,mon1,year0,year1)beginif(lock=“000”)thena0end if。if(lock=“000”)thena0end if。if(lock=“001”)thena0end if。if(lock=“101”)thena0end if。if(lock=“110”)thena0end if。if(lock=“111”)thena0end if。if(lock=“010”)then a0a0end if。if(lock=“100”)thena0end if。end process。end Behavioral。library IEEE。use 。use 。use 。Unment the following lines to use the declarations that areprovided for instantiating Xilinx primitive UNISIM。use 。use 。entity month_year isPort(clk0,clk1,ce : in std_logic。lock : in std_logic_vector(2 downto 0)。up : in std_logic。mon0,mon1 : buffer std_logic_vector(3 downto 0)。year0,year1 : buffer std_logic_vector(3 downto 0))。end month_year。architecture Behavioral of month_year is signal Ty0,Ty1,Tm0,Tm1:std_logic_vector(3 downto 0)。signal clk:std_logic。beginTy0beginif(lock=“000” or lock=“001”)thenclkelse clkend if。end process u1。u2:process(clk,ce)begin if rising_edge(clk)thenif(ce=39。139。)thenif(lock=“000”)or(lock=“001”)or(lock=“011” and up=39。139。)thenadd_month(Tm0,Tm1,mon0,mon1)。end if。if(lock=“011” and up=39。039。)thensub_month(Tm0,Tm1,mon0,mon1)。end if。if(lock=“000” or lock=“001”)thenif(mon0=“0010” and mon1=“0001”)thenadd_year(Ty0,Ty1,year0,year1)。end if。end if。if(lock=“010” and up=39。139。)thenadd_year(Ty0,Ty1,year0,year1)。end if。if(lock=“010” and up=39。039。)thensub_year(Ty0,Ty1,year0,year1)。end if。end if。end if。end process u2。end Behavioral。library ieee。use 。use 。package pac isprocedure add_year(oldyear0,oldyear1:in std_logic_vector。signal newyear0:out std_logic_vector。signal newyear1:out std_logic_vector)。procedure add_month(oldmonth0,oldmonth1:in std_logic_vector。signal newmonth0:out std_logic_vector。signal newmonth1:out std_logic_vector)。procedure sub_month(oldmonth0,oldmonth1:in std_logic_vector。signal newmonth0:out std_logic_vector。signal newmonth1:out std_logic_vector)。procedure sub_year(oldyear0,oldyear1:in std_logic_vector。signal newyear0:out std_logic_vector。signal newyear1:out std_logic_vector)。procedure Feb_add_day(oldday0,oldday1:in std_logic_vector。ty0:in std_logic_vector(1 downto 0)。ty1:in std_logic。signal newday0:out std_logic_vector。signal newday1:out std_logic_vector)。procedure Feb_sub_day(oldday0,oldday1:in std_logic_vector。ty0:in std_logic_vector(1 downto 0)。ty1:in std_logic。signal newday0:out std_logic_vector。signal newday1:out std_logic_vector)。procedure oddmonth_add_day(oldday0,oldday1:in std_logic_vector。signal newday0:out std_logic_vector。signal newday1:out std_logic_vector)。procedure oddmonth_sub_day(oldday0,oldday1:in std_logic_vector。signal newday0:out std_logic_vector