【正文】 clr c mov a,res_1 rlc a mov res_1,a mov a,res_2 rlc a mov res_2,a mov a,res_3 rlc a mov res_3,a mov a,res_4 rlc a mov res_4,a mov a,res_5 rlc a mov res_5,a mov a,res_6 rlc a mov res_6,a mov a,res_7 rlc a mov res_7,a mov a,res_8 rlc a mov res_8,a mov a,tmp_1 rlc a mov tmp_1,a mov a,tmp_2 rlc a mov tmp_2,a mov a,tmp_3 rlc a mov tmp_3,a mov a,tmp_4 rlc a mov tmp_4,a mov a,tmp_5 rlc a mov tmp_5,a mov a,tmp_6 rlc a mov tmp_6,a mov a,tmp_7 rlc a mov tmp_7,a mov a,tmp_8 rlc a mov tmp_8,a clr c mov a,tmp_1 subb a,tsq_1 mov tmp_1,a mov a,tmp_2 subb a,tsq_2 mov tmp_2,a mov a,tmp_3 subb a,tsq_3 mov tmp_3,a mov a,tmp_4 subb a,tsq_4 mov tmp_4,a mov a,tmp_5 subb a,0 mov tmp_5,a mov a,tmp_6 subb a,0 mov tmp_6,a mov a,tmp_7 subb a,0 mov tmp_7,a mov a,tmp_8 subb a,0 mov tmp_8,a jnc div_2 mov a,tmp_1 add a,tsq_1 mov tmp_1,a mov a,tmp_2 addc a,tsq_2 mov tmp_2,a mov a,tmp_3 addc a,tsq_3 mov tmp_3,a mov a,tmp_4 addc a,tsq_4 mov tmp_4,a mov a,tmp_5 addc a,0 mov tmp_5,a mov a,tmp_6 addc a,0 mov tmp_6,a mov a,tmp_7 addc a,0 mov tmp_7,a mov a,tmp_8 addc a,0 mov tmp_8,a ajmp div_3 div_4: ajmp div_1 div_2: inc res_1 div_3: djnz R4,div_4 ret 。***********************************************。4字節(jié)hex(res4~1)轉(zhuǎn)4字節(jié)壓縮bcd(tmp4~1),。并將非壓縮的BCD送到BCD_REG+0~7中。占用153字節(jié),耗時(shí)1059周期。影響資源r4,acc,cy。***********************************************hex_bcd: 。二進(jìn)制轉(zhuǎn)BCD mov r4,32 mov tmp_1,0 mov tmp_2,0 mov tmp_3,0 mov tmp_4,0 loop: clr c mov a,res_1 rlc a mov res_1,a mov a,res_2 rlc a mov res_2,a mov a,res_3 rlc a mov res_3,a mov a,res_4 rlc a mov res_4,a mov a,tmp_1 addc a,tmp_1 da a mov tmp_1,a mov a,tmp_2 addc a,tmp_2 da a mov tmp_2,a mov a,tmp_3 addc a,tmp_3 da a mov tmp_3,a mov a,tmp_4 addc a,tmp_4 da a mov tmp_4,a djnz r4,loop mov bcd_reg,tmp_1 anl bcd_reg,0fh mov bcd_reg+1,tmp_1 anl bcd_reg+1,0f0h mov a,bcd_reg+1 swap a mov bcd_reg+1,a mov bcd_reg+2,tmp_2 anl bcd_reg+2,0fh mov bcd_reg+3,tmp_2 anl bcd_reg+3,0f0h mov a,bcd_reg+3 swap a mov bcd_reg+3,a mov bcd_reg+4,tmp_3 anl bcd_reg+4,0fh mov bcd_reg+5,tmp_3 anl bcd_reg+5,0f0h mov a,bcd_reg+5 swap a mov bcd_reg+5,a mov bcd_reg+6,tmp_4 anl bcd_reg+6,0fh mov bcd_reg+7,tmp_4 anl bcd_reg+7,0f0h mov a,bcd_reg+7 swap a mov bcd_reg+7,a retdelay_cl: 。延時(shí)~ mov r7,250dl_0: mov r6,0dl_1: mov r5,0 djnz r5,$ djnz r6,dl_1 djnz r7,dl_0 ret end附錄二：VHDL程序、頂視圖程序—easter1LIBRARY IEEE。USE 。USE 。ENTITY etester1 ISPORT (BCLK: IN STD_LOGIC。 TCLK: IN STD_LOGIC。 CLR: IN STD_LOGIC。 CL: IN STD_LOGIC。 SPUL: IN STD_LOGIC。 START: OUT STD_LOGIC。 EEND: OUT STD_LOGIC。 SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0)。 DATA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0))。END etester1。ARCHITECTURE behav OF etester1 ISCOMPONENT chufaPORT (TCLK1: IN STD_LOGIC。 CLR1: IN STD_LOGIC。 CL1: IN STD_LOGIC。 ENA5: OUT STD_LOGIC。 ENA: OUT STD_LOGIC)。END COMPONENT。COMPONENT logic1PORT (TCLK2: IN STD_LOGIC。 CLR2: IN STD_LOGIC。 CL2: IN STD_LOGIC。 SPUL1: IN STD_LOGIC。 EEND1: OUT STD_LOGIC。 ENA1: IN STD_LOGIC。 BENA: OUT STD_LOGIC)。END COMPONENT。COMPONENT counterPORT (BCLK3: IN STD_LOGIC。 TCLK3: IN STD_LOGIC。 CLR3: IN STD_LOGIC。 BENA1: IN STD_LOGIC。 ENA2: IN STD_LOGIC。 SEL1: IN STD_LOGIC_VECTOR(2 DOWNTO 0)。 DATA1: OUT STD_LOGIC_VECTOR(7 DOWNTO 0))。END COMPONENT。COMPONENT select1PORT (SEL1: IN STD_LOGIC_VECTOR(2 DOWNTO 0)。 BZQ1: IN STD_LOGIC_VECTOR(31 DOWNTO 0)。 TSQ1: IN STD_LOGIC_VECTOR(31 DOWNTO 0)。 DATA1: OUT STD_LOGIC_VECTOR(7 DOWNTO 0))。END COMPONENT。SIGNAL ENA8: STD_LOGIC。SIGNAL BENA8: STD_LOGIC。BEGINU1: chufa PORT MAP(TCLK1=TCLK,CLR1=CLR,CL1=CL,ENA5=START,ENA=ENA8)。U2: logic1 PORT MAP(TCLK2=TCLK,CLR2=CLR,CL2=CL,SPUL1=SPUL,EEND1=EEND,ENA1=ENA8,BENA=BENA8)。U3: counter PORT MAP(BCLK3=BCLK,TCLK3=TCLK,CLR3=CLR,BENA1=BENA8,ENA2=ENA8,SEL1=SEL,DATA1=DATA)。END ARCHITECTURE behav。 、觸發(fā)器模塊程序chufaLIBRARY IEEE。USE 。USE 。ENTITY chufa ISPORT (TCLK1: IN STD_LOGIC。 CLR1: IN STD_LOGIC。 CL1: IN STD_LOGIC。 ENA5: OUT STD_LOGIC。 ENA: OUT STD_LOGIC)。END chufa。ARCHITECTURE a OF chufa ISSIGNAL ENA6: STD_LOGIC。BEGINPROCESS(TCLK1,CLR1)BEGIN IF CLR1=39。139。 THEN ENA6 =39。039。 ELSIF TCLK139。EVENT AND TCLK1=39。139。 THEN ENA6 =CL1。 END IF。ENA=ENA6。ENA5=ENA6。END PROCESS。END A。、計(jì)數(shù)器模塊程序counterLIBRARY IEEE。USE 。USE 。ENTITY counter ISPORT (BCLK3: IN STD_LOGIC。 TCLK3: IN STD_LOGIC。 CLR3: IN STD_LOGIC。 BENA1: IN STD_LOGIC。 ENA2: IN STD_LOGIC。 SEL1: IN STD_LOGIC_VECTOR(2