【正文】 multichip FPGA can support a PROM Programming。 serial mode can use the serial PROM programming the FPGA。 peripheral mode the FPGA as a micro peripherals of the processor, microprocessor programming. How to achieve rapid timing closure, to reduce power consumption and costs, optimize the clock management and reduce the plexity of issues such as FPGA and PCB concurrent design, has been using the FPGA system designers need to consider the key issues. Now, with the FPGA to the higher density, greater capacity, lower power consumption and integration in the direction of more IP development, system design engineers to benefit from these excellent performance at the same time, have to face the the FPGA unprecedented performance and ability level and the new design challenges. For example, recently launched by leading FPGA vendors Xilinx Virtex5 family using 65nm technology can deliver up to 330,000 logic cells, 1,200 I / O and hard IP block. The large capacity and density of the plex wiring bees more unpredictable, and the resulting more serious problem of timing closure. In addition, the integration for different applications and a larger number of logic functions, DSP, embedded processing and interface modules, clock management and voltage allocation problem bees more difficult. Fortunately, the FPGA vendors, EDA tool vendors are working together to solve unique design challenges of 65nm FPGAs. Not long ago, Synplicity and Xilinx announced the formation of large capacity timing closure joint working group designed to maximize help to system design engineers a faster, more efficient application of 65nm FPGA devices. Synthesis tool launched by the design software provider Magma Blast, the FPGA can help to establish an optimized layout, speed up the convergence of timing. Recently, the FPGA configuration has diversified FPGA design of Note Whether you are a logic designers, hardware engineers or systems engineers, or even to have all these titles, as long as you use in any plex system of a highspeed and multiprotocol FPGA, you most likely need to work to solve the device configuration, power management, IP integration, signal integrity and some key design issues. However, you do not have to alone to face these challenges every day because in the current industryleading FPGA pany39。s application engineers face these problems, and they have made a number of design guidelines will make your design work has bee easier and solutions. I / O signal distribution Can provide the most multifunctional pin, I / O standard, termination schemes and differential FPGA signal distribution with the most plex design guidelines. Altera39。s FPGA device design guidelines (because it implements is easier), but the Xilinx FPGA design guidelines is very plex. But no matter what kind of situation, I / O pin assignment signal, there are some mon steps to keep in mind: (1) Use a spreadsheet to list all the plans of the signal distribution, as well as their important properties, such as I / O standard voltage termination method and the associated clock. (2) check the manufacturer39。s / region patibility guidelines. Consider using a spreadsheet to develop the layout of the FPGA to determine which pin is mon, and which is dedicated, which support differential signal on the global and local clock, which requires the reference voltage. (4) the use of electronic data table information and region patibility guidelines, first be allocated to the largest signal of the limited extent to the pin, the final distribution by the least restrictive. For example, you may need to first be allocated to the serial bus clock signal, because they are usually assigned to specific pins. (5) In accordance with the level of restricted redistribution of the signal bus. At this stage, it may be necessary to carefully weigh the simultaneous switching output (SSO) and is not patible with the I / O standards, especially when you have a lot of highspeed output, or use several different I / O standards. If your design requires local / regional clock, you will probably need to use highspeed bus near the pin, it is best to remember this request in advance to avoid last can not be arranged by the most appropriate pin. If a particular block the selected I / O standard reference voltage signal, remember to not to assign these pins. The distribution of the differential signal is always first in singleended signal. If an FPGA chip termination, it may also apply to other patibility rules. (6) The allocation of the remaining signal in the right place. At this stage, consider writing an HDL file contains only the port assignment. And then by using the tools provided by the supplier or use a text editor to manually create a restricted file I / O standards and SSO to increase the necessary support information. These documents are ready, you can run the place and route tools to confirm whether to ignore a number of criteria or do a wrong allocation. This will give you in the initial stages of design and layout engineers to work together to jointly plan the PCB traces, redundancy planning, heat dissipation and signal integrity. FPGA tools may be able to provide assistance in these areas and to help you solve these problems, so you must make sure to understand your toolkit. You consult a layout expert later time, the more likely you need to deal with plex problems and design iterations, and these may be avoided by some preliminary analysis. Once you achieve a satisfactory signal distribution, you have to limit the file lock. CMOSbased design is the main consumption of three types of shear rate: internal (short circuit), leakage (static) and switch (capacitor). When the gate transients, short circuit between the VDD and ground connection to internal power consumption. Leakage power CMOS process, a mon parasitic effects caused. The switching power is caused by the load capacitance discharge. Switching power and short circuit power consumption together referred to as the dyna