【正文】 ternal pull一ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (lip) because of the internal 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVX@DPTR). In this application, Port 2 uses strong internal pull一ups when emitting 1s. During accesses to external data memory that use 8bit addresses (MOVX@RI), Port 2 emits the contents of the P2 Special Function 2 also receives the highorder address bits and some control signals during Flash programming and verification.Port 3：Port 3 is an 8一bit bidirectional I/O port with internal pull一ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lip) because of the 3 receives some control signals for Flash programming and 3 also serves the functions of various special features of the AT89S51，as shown in the following table.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may beused for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external program the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on should be strapped to Vcc for internal program pin also receives the 12volt programming enable voltage (VPP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifierSpecial Function Registers：Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate software should not write 1 s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Interrupt Registers:The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.Dual Data Pointer Registers:To facilitate accessing both internal and external data memory, two banks of 16bit Data Pointer Registers are provided: DPO at SFR address locations 82H83H and DP1 at DPS=0 in SFR AUXR1 selects DPO and DPS=1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag:The Power Off Flag (POF) is located at bit 4 () in the PCON SFR. POF is set to 1”during power up. It can be set and rest under software control and is not affected by reset.Memory Organization：MCS51 devices have a separate address space for Program and Data Memory. Up to 64Kbytes each of external Program and Data Memory can be addressed.Program Memory：If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51，if EA is connected to Vcc, program fetches to addresses OOOOH through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.Data Memory：The AT89S51 implements 128 bytes of onchip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.Watchdog Timer (Onetime Enabled with Resetout)：The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14一bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01 EH and OE1 H in sequence to the WDTRST register (SFR location OA6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.Timer 0 and 1：Timer 0 and Timer 1 is a 16bit Timer/Coun