【正文】 虛心的向老師和同學求教,爭取在師老師的指導下出色的完成畢業(yè)設計。 指導老師: 師公社 學生: 陳媛 2022 年 3 月西 安 工 業(yè) 學 院 畢 業(yè) 論 文 328．2 中期報告《運動控制智能模擬負載》——硬件部分畢 業(yè) 設 計 中 期 報 告一、題目 　運動控制的智能模擬負載系統(tǒng)，主要是用單片機控制來實現(xiàn)對運動控制系統(tǒng)實驗中負載對象及其變化規(guī)律的要求。此項畢業(yè)設計囊括了專業(yè)電工、電子、電力電子技術(shù)，MCS—51 系列單片機工作原理及應用技術(shù)， PROTEL 技術(shù)等學科知識。二、系統(tǒng)結(jié)構(gòu)的簡單框圖 該系統(tǒng)旨在利用單片機實現(xiàn)對負載對象變化的控制，其主要由單片機，SPI 串行總線的 E2PROM 參數(shù)存儲，鍵盤，帶光電耦合的 RS485 接口芯片，顯示及常規(guī)可靠性接地設計組成，具體如下：三、系統(tǒng)主要器件的選取及其設計的簡要介紹* AT89C51 單片機AT89C51 是一種帶有 4KBFlash 可編程、可擦除只讀存儲器（EEPROM）的低壓、高性能 8 位 CMOS 微型計算機。通過在單塊芯片上組合通用的 CPU 和 Flash 存儲器。在需要I/O 線不多的控制場合，選用它作為核心控制芯片，可使電路極大的簡化，而且程序的西 安 工 業(yè) 學 院 畢 業(yè) 論 文 33編寫及固化也相當方便、靈活。* X5043/45 接口芯片在該系統(tǒng)中，為解決電源開斷、瞬時電壓不穩(wěn)等不安全因素，將會造成系統(tǒng)死機、信息丟失、運行不穩(wěn)定等故障，實現(xiàn)系統(tǒng)安全可靠、穩(wěn)定、實時運行，故采用 X5045 芯片。X5045 是將可編程看門狗、電壓監(jiān)控、E 2PROM 集于一體的多功能芯片，該芯片具有體積小、占用 I/O 少等優(yōu)點，應用于系統(tǒng)中可以簡化單片機系統(tǒng)的設計，并完善其性能。* RS—485標準通訊口串行通信接口是指設備之間的接口。我們最熟悉的關于串行通信接口的名詞可能就是 COM 與 USB 了，因為它們都是當代 PC 機必備的串行通信接口。在使用 RS—485 總線時，如果簡單地按常規(guī)方式設計電路，在實際工程中可能有通信數(shù)據(jù)收發(fā)的可靠性問題。隔離問題：通過光電耦合器件發(fā)作用有利于提高傳輸速率。* 顯示部分的硬件設計 （未完成）LED 顯示器中的發(fā)光二極管共有兩種連接方法，本方案采用共陽極接法。在一般情況下，單片機使用并行驅(qū)動的方式進行 LED 的顯示。并行驅(qū)動的結(jié)構(gòu)較為簡單，并且在單片機的選擇上，采用了 AT89C51，它有 32 條 I/O 口線，采用并行驅(qū)動方式，接口完全夠用?！? 顯示器的驅(qū)動芯片的類型要根據(jù)電路的具體參數(shù)的計算進行選取，現(xiàn)在還未完成。* 鍵盤程序（未完成） 該鍵盤中設置了三個鍵，用于設置系統(tǒng)中的調(diào)節(jié)負載輸出變化的參數(shù)。* 負載部分 （未完成）目前，系統(tǒng)的大部分硬件設計已初步確定，還有具體的元件型號、參數(shù)的確定，按鍵的處理部分及負載的驅(qū)動和隔離還未完成，擬定在 5 月中旬完成并進行完善，以便很好的進行下一步的工作。西 安 工 業(yè) 學 院 畢 業(yè) 論 文 348．3 相關外文資料翻譯Complete Model of E2PROM Memory Cell for Circuit SimulationAbstractE2PROM memory devices are widely used in embedded applications. For an efficient design flow, a correct modeling of these memory cells in every operation condition bees more and more important, especially due to power consumption limitations. Although E2PROM cells are being used for a long time, very few pact models have been developed. Here，we present a plete pact model based on an original procedure to calculate the floating gate potential in dc conditions, without the need of any capacitive coupling coefficient. This model is designed as a modular structure, so to simplify program/erase and reliability simulations. Program/erase and leakage currents are included by means of simple voltagecontrolled current sources implementing their analytical expression. It can be used to simulate memory cells both during read operation (dc conditions) and during program and erase (transient conditions) giving always very accurate results. We will show also that, provided good description of degradation mechanisms, the same model can be used also for reliability simulations, predicting charge loss due to tunnel oxide degradation.Index TermsCircuit simulation, puter aided design(CAD), integrated circuits, modeling, semiconductor memories.I. INTRODUCTIONIn the semiconductor industry, “modeling” and “characterization” have different meanings. Compact model means an analytic model of the electrical behavior of a circuit element, as used in a SPICElike circuit simulator, and characterization means the procedure by which the parameters of pact model are determined for devices in a particular integrated circuit (IC) manufacturing technology.Compact models should be formulated physically, as functions of both the fundamental process parameters that control device electrical behavior and geometric layout parameters associated with a device (both adjustable layout parameters, such as device length and width 西 安 工 業(yè) 學 院 畢 業(yè) 論 文 35and technologydependent layout parameters derived from design rules, such as spacing between active areas and implant areas, etc.). There are three main reasons for preferring physically based pact models [1]. First, they provide the best basis for statistical modeling[2]. Second, they provide the best basis for mismatch modeling. Third, during the life cycle of a manufacturing technology there are changes, both in process flow and in design rules, that require to quickly retarget the design library.Although the importance of E2PROM memory cells has grown, very few pact models have been developed to be used in SPACElike simulators [3] to study dc and transient behavior of plex circuits containing E2PROM cells. E2PROM cells are based on floating gate (FG) devices, which are metaloxidesemiconductor (MOS) transistors where a conductive layer is interleaved between gate and channel and it is surrounded by insulator. The conductive layer is called FG. These devices’ threshold voltage can be changed by injecting and/or extracting charge in/from the FG. Because of the lack of reliable pact models in the industry plex circuits are usually simulated replacing FG memory devices with MOS transistors, whose threshold voltage is “manually” changed to simulate the erased and programmed states of the memory cell.Different from pact models proposed in the past [3], [4], the plete pact model of E2PROM cell we have developed is based on an original method to calculate FG potential in dc conditions [5]. This method does not use the fixed capacitive coupling coefficients any more and it is based on the solution of the charge balance equation at the FG node (which improves the FG voltage estimate, ., the overall modeling of the memory device) and on charge equations of the MOS transistor. Moreover, the pact model is designed to be modular, ., any transient phenomena (program, erase, leakage) can be included by adding a voltage controlled current source