基于fpga的任意信號(hào)發(fā)生器設(shè)計(jì)外文翻譯-其他專業(yè)-資料下載頁(yè)
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【導(dǎo)讀】數(shù)字信號(hào)發(fā)生器已成為現(xiàn)代測(cè)量領(lǐng)域應(yīng)用最為廣泛的通用儀器之一，代表了信。號(hào)源的發(fā)展方向。而隨著大規(guī)?？删幊踢壿嬈骷﨔PGA的發(fā)展以及可編程片上系統(tǒng)。率和相位差顯示。設(shè)計(jì)中采用的是直接數(shù)字頻率合成技術(shù)，該技術(shù)是一項(xiàng)。關(guān)鍵的數(shù)字技術(shù)，能很好的實(shí)現(xiàn)信號(hào)在幅度，頻率以及相位等方面的移動(dòng)。EDA軟件為工具，采用VHDL語言，滿足了對(duì)數(shù)字信號(hào)控制的更高要求。信號(hào)發(fā)生器相比具有更高的可靠性、實(shí)時(shí)性、運(yùn)算速度高以及集成度高等特點(diǎn)。信號(hào)，使系統(tǒng)性能穩(wěn)定可靠。然而，隨著FPGA的資源合理使用，使用FPGA. 進(jìn)行數(shù)字化多通道模擬波形成為了一種可能。模擬輸入均直接連接到FPGA的輸入引腳。輸出引腳，以便生成定期參考電壓斜坡。差分輸入緩沖器由于其有效的大的輸入電壓范圍成為了很好的比較器。計(jì)劃，在較大的FPGA資。被誤認(rèn)為是參照基于雙斜坡原則的威爾金森ADC。器，這些解串器只能由高端FPGA系列提供。器的一致的傳播延遲，從而獲得均勻的位寬，最大限度地減少微分非線性。
【正文】 The reference voltage shown in Fig. 6 has a short time constant. The exponential reference voltage samples the input waveform shown in Fig. 7(a). (Note that the oscilloscope time scales for Fig. 6 and 7(a) are different but the voltage scales are them same.) It can be seen from Fig. 7(b) that a smoother waveform is digitized by the trailing ramp. This test shows a 6 bit measurement range at M samples/sec while the dynamic range of the trailing ramp samples is approximately 8 bits. Passive ponents are chosen for the ramping reference voltage generation work primarily for simplicity. The ramping voltage from passive RC work is intrinsically nonlinear which sometimes is viewed as a disadvantage. In FPGA, however, correcting nonlinearity is merely a transform via a lookup table. In our example here, the exponential voltage ramp can be further used to increase measurement dynamic range, which bees an advantage. In many applications, only relative precision in a measurement is needed, ., finer measurements are only needed for small signals while for larger signals, coarser measurements are sufficient. IV. CONCLUSION Multisampling based TDC has been studied, implemented in low cost FPGA and bench tested. Three applications: multichannel FPGAonly TDC, FPGA only ADC and a deserializer ―Digital Phase Follower‖ are discussed. Interfacing FPGA directly with the continuous variables (arrival time and input voltage) eliminates external devices and simplifies system design. The measurement made can be processed immediately in the FPGA without having to pass data via on board busses. REFERENCES [1] P. Allen amp。 D. Holberg, CMOS Analog Circuit Design, Second Edition, New York, New York: Oxford University Press, 2021. [2] B. G. Tomov amp。 J. A. Jensen, ―A new architecture for a singlechip multichannel beamformer based on a standard FPGA,‖ in Ultrasonics Symposium, 2021 IEEE, 710 Oct. 2021 Page(s):1529 1533 . [3] D. Wilkinson, ―Blood, Birds, and the Old Road,‖ in Annu. Rev. Nucl. Part. Sci. 1995, Pages 139, vol. 45. [4] G. Blanar, K. Roberts amp。 R. Sumner, ―A new concept for a multirange low cost calorimeter ADC,‖ in Nuclear Science Symposium and Medical Imaging Conference, 1994 IEEE Conference Record, 30 5 Nov. 1994 Page(s):999 1001 . [5] Jinyuan Wu, Zonghan Shi amp。 I. Y. Wang, ―Firmwareonly implementation of timetodigital converter (TDC) in field programmable gate array (FPGA),‖ in Nuclear Science Symposium Conference Record, 2021 IEEE, 1925 Oct. 2021 Page(s):177 181 Vol. 1. [6] S. S. Junnarkar, et. al., ―An FPGAbased, 12channel TDC and digital signal processing module for the RatCAP scanner,‖ in Nuclear Science Symposium Conference Record, 2021 IEEE, Volume 2, 2329 Oct. 2021 Page(s):919 923. [7] M. D. Fries amp。 J. J. Williams, ―Highprecision TDC in an FPGA using a 192 MHz quadrature clock,‖ in Nuclear Science Symposium Conference Record, 2021 IEEE, 1016 Nov. 2021 Page(s):580 – 584 vol. 1. [8] Altera Corp., ―Cyclone FPGA Family Data Sheet‖, (2021) available via: { [9] Altera Corporation, ―Cyclone II Device Handbook‖, (2021) available via: { [10] Jinyuan Wu, ―Digital Phase Follower Deserializer in LowCost FPGA‖, BTeV Document 3295v1, Fermi National Accelerator Laboratory, (2021), available online: { public/DocDB/ShowDocument?docid=3295} [11] Nick Sawyer, ―Data Recovery‖, Xilinx Application Note 224, (2021), available via: { [12] Jinyuan Wu, ―How to Design Compact FPGA Functions—Resource Awareness Design Practices‖, (2021) available via: { W/Projects/ckm/adc/ }
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