【文章內(nèi)容簡介】 qi。architecture Behavioral of fenpinqi issignal current_state : STD_LOGIC_VECTOR(15 downto 0):=(others=39。039。)。signal new_state : STD_LOGIC_VECTOR(15 downto 0):=(others=39。039。)。beginprocess(current_state)beginif current_state=49999 thennew_state=(others =39。039。)。elsenew_state= current_state+1。18 / 39end if。end process。process(clk_in)beginif falling_edge(clk_in)thencurrent_state=new_state。end if。end process。clk=current_state(15)。end Behavioral。 計數(shù)器模十計數(shù)器：library IEEE。use 。use 。entity m_10 isport(clk,rst : in std_logic。carry_in : in std_logic。carry_out : out std_logic。count : out std_logic_vector(3 downto 0))。end m_10。architecture Behavioral of m_10 issignal c_state,n_state:std_logic_vector(3 downto 0)。beginP1:process(carry_in,c_state)beginif carry_in=39。139。 thenif c_state=9 thenn_state=0000。elsen_state=c_state+1。end if。19 / 39elsen_state=c_state。end if。end process。P2:process(clk,rst)beginif rst=39。139。 thenc_state=0000。elsif falling_edge (clk) thenc_state=n_state。end if。end process。count=c_state。carry_out=39。139。 when carry_in=39。139。 and c_state=9 else 39。039。end Behavioral。模六計數(shù)器：library IEEE。use 。use 。entity m_6 isport(clk,rst : in std_logic。carry_in : in std_logic。carry_out : out std_logic。count : out std_logic_vector(3 downto 0))。end m_6。architecture Behavioral of m_6 issignal c_state,n_state:std_logic_vector(3 downto 0)。beginP1:process(carry_in,c_state)beginif carry_in=39。139。 thenif c_state=5 thenn_state=0000。elsen_state=c_state+1。end if。elsen_state=c_state。20 / 39end if。end process。P2:process(clk,rst)beginif rst=39。139。 thenc_state=0000。elsif falling_edge (clk) thenc_state=n_state。end if。end process。count=c_state。carry_out=39。139。 when carry_in=39。139。 and c_state=5 else 39。039。end Behavioral。計數(shù)器模塊：library IEEE。use 。entity counter is Port ( rst : in STD_LOGIC。 clk : in STD_LOGIC。 ena : in STD_LOGIC。 count6 : out STD_LOGIC_VECTOR (3 downto 0)。 count5 : out STD_LOGIC_VECTOR (3 downto 0)。 count4 : out STD_LOGIC_VECTOR (3 downto 0)。 count3 : out STD_LOGIC_VECTOR (3 downto 0)。 count2 : out STD_LOGIC_VECTOR (3 downto 0)。 count1 : out STD_LOGIC_VECTOR (3 downto 0))。end counter。architecture Behavioral of counter isCOMPONENT m_10PORT(clk : IN std_logic。rst : IN std_logic。carry_in : IN std_logic。 carry_out : OUT std_logic。count : OUT std_logic_vector(3 downto 0))。END COMPONENT。COMPONENT m_6PORT(21 / 39clk : IN std_logic。rst : IN std_logic。carry_in : IN std_logic。 carry_out : OUT std_logic。count : OUT std_logic_vector(3 downto 0))。END COMPONENT。signal cry0,cry1,cry2,cry3,cry4,cry5 : std_logic。beginu0: m_10 PORT MAP(clk = clk,rst = rst,carry_in = ena,carry_out = cry0,count = open)。u1: m_10 PORT MAP(clk = clk,rst = rst,carry_in = cry0,carry_out = cry1,count = count1)。u2: m_10 PORT MAP(clk = clk,rst = rst,carry_in = cry1,carry_out = cry2,count = count2)。u3: m_10 PORT MAP(clk = clk,rst = rst,carry_in = cry2,carry_out = cry3,count = count3)。u4: m_6 PORT MAP(clk = clk,22 / 39rst = rst,carry_in = cry3,carry_out = cry4,count = count4)。u5: m_10 PORT MAP(clk = clk,rst = rst,carry_in = cry4,carry_out = cry5,count = count5)。u6: m_6 PORT MAP(clk = clk,rst = rst,carry_in = cry5,carry_out = open,count = count6)。end Behavioral。測試程序關(guān)鍵部分： stim_proc: process begin rst = 39。139。ena = 39。139。 wait for ms。rst = 39。039。 wait for clk_period*1234。ena = 39。039。 wait for clk_period*87。ena = 39。139。 wait。 end process。END。仿真結(jié)果：23 / 3924 / 39 掃描控制顯示電路25 / 39多路復(fù)用模塊：library IEEE。use 。entity fu_yong is Port ( scan_in6 : in STD_LOGIC_VECTOR (3 downto 0)。 scan_in5 : in STD_LOGIC_VECTOR (3 downto 0)。 scan_in4 : in STD_LOGIC_VECTOR (3 downto 0)。 scan_in3 : in STD_LOGIC_VECTOR (3 downto 0)。 scan_in2 : in STD_LOGIC_VECTOR (3 downto 0)。 scan_in1 : in STD_LOGIC_VECTOR (3 downto 0)。 s_xuan : in STD_LOGIC_VECTOR (2 downto 0)。 BCD : out STD_LOGIC_VECTOR (3 downto 0))。end fu_yong。architecture Behavioral of fu_yong isbeginprocess(scan_in6,scan_in5,scan_in4,scan_in3,scan_in2,scan_in1,s_xuan)begincase s_xuan isWHEN 000 = BCD =scan_in6。WHEN 001 = BCD =scan_in5。WHEN 010 = BCD =1111。26 / 39WHEN 011 = BCD =scan_in4。WHEN 100 = BCD =scan_in3。WHEN 101 = BCD =1111。WHEN 110 = BCD =scan_in2。WHEN 111 = BCD =scan_in1。when others= BCD = 1111。end case。end process。end Behavioral。三八譯碼器模塊:library IEEE。use 。use 。entity m_3 isport(clk : in STD_LOGIC。 s_xuan : out STD_LOGIC_VECTOR (2 downto 0))。end m_3 。architecture Behavioral of m_3 issignal c_state,n_state:std_logic_vector(2 downto 0):=000。beginP1:process(c_state)beginif c_state=7 thenn_state=000。elsen_state=c_state+1。end if。end process。P2:process(clk)beginif falling_edge (clk) thenc_state=n_state。end if。end process。 s_xuan=c_state。end Behavioral。27