cypresspsoc可配置混合信號片上系統(tǒng)簡介(編輯修改稿)
2024-11-17 16:04 本頁面
【文章內(nèi)容簡介】 nctional Level Not Programmed at the Gate Level 18 Analog PSoC Blocks CA I nput sREF I nput sSNOBUSCBUSA .I NCCInput sCB I nput sA .S IG NA .REFCC0 31 CCB0 31 CCA0 31 CCF1 6 32 Cf1*! A Zf2f2f2+ A Zf1*A Zf1(f2+ ! A Z) * N1f1* N0P W ROS * f2BCSf1P o r t I n p u t sB l o c O u t p u t sVD DC B U SB l o c I n p u t sP [ 2 : 0 ]A G N DRESISTORMATRIXC E NA G N DO B U SVR E FN [ 2 : 0 ]O B U SVR E F SP W RC CGC T B l o cA G N D VS SS CB l o cF 2T [ 2 : 0 ]RVR E F +A G N DC PC KF [ 1 : 0 ]O SGO U TG O U TL O U TP ( I N )VR E F Continuous Time Twelve Analog PSoC Blocks Available Three Types: ?Continuous Time (4) ?Switch Capacitor C (4) ?Switch Capacitor D (4) C A I n p u t sR E F I n p u t sO B U SC B U SA . I NC A R RC B I n p u t sA . S I G NA . R E FB . I NC C0 3 1 CC B0 3 1 CC A0 3 1 CC F1 6 3 2 Cf2f1* A Zf1( f2+ ! A Z ) * F . I N 1f1* F . I N 0P W RO S * f2BC Sf1* ! A Zf2+ A Zf1* B . S Wf2+ ! B . S Wf1* B . S Wf2+ ! B . S WSwitched Capacitor D Switched Capacitor C 19 User Modules Preconfigured and Precharacterized Digital and Analog PSoC Blocks Analogous to Onchip Peripherals ?Timer Counters – PWM’s ?UART – SPI ?A/D –DAC’s SAR Defines the Register Bits for Initial Configuration Selected via Double Click in IDE User Modules Include ?Application Programmer Interfaces (APIs) ?Interrupt Service Routines (ISRs) ?Specific UM Data Sheets 20 Digital User Modules 8, 16, 24, 32bit Timer 8, 16, 24, 32bit Counter 8, 16bit PWM 8, 16bit Dead Band Generator ?(2 Phase Underlapped Clock) Pseudo Random Source (PRS) Cyclic Redundancy Check (CRC) Generator I2C Master I2C Slave SPI Master SPI Slave Full Duplex UART IrDA receiver and transmitter 21 Analog User Modules A/D Converters ? 8bit Successive Approximation ? 8bit Delta Sigma
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