著名半導(dǎo)體公司dft_atpg內(nèi)部培訓(xùn)資料(存儲(chǔ)版)
【正文】 ct or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. DFT Signals ?DFT signals ? Ipt_mode_scan_xxx ? Ipt_se_xxx ? Ipt_se_async_xxx ? Ipt_se_gatedclkn/p_xxx ? Ipt_si/so_xxx ? Ipt_dbg_tck_xxx ? Ipt_dbg_trst_xxx ? Ipt_dbg_tms_xxx ? Ipt_dbf_tdi_xxx ? Ipt_dbg_tdo_xxx Please refer to Section of WMSG CD/MAD IP DFT Guidelines TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. Qamp。A ?What’s it? ? DFT ? Structured DFT ? ATPG ?Terminology in Scan ? Scan cell ? Scan chain ? Scan procedure ? Scan waveform ? Scan type ? Scan fault model ? Scan Coverage TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. Agenda ? DFT Rules ? Combinational Loop ? Asynchronous Reset ? Tristate Bus Contention ? Clock Dividers ? Clock Gating ? DFT signals ? For Scan ? For debug ? Soft IP tasks and deliverables ? Scripts and Demos ? Qamp。 Tristate But ?Combinational Loop ? Notice that the A=1, B=0, C=1 state causes unknown (oscillatory) behavior, which poses a testability problem. ? It should be avoid if possible. ?Tristate Bus Contention ? Tristate Bus is not permitted inside chip. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. SCAN Procedure ?The operating procedure of the scan circuitry is as follows: ? 1. Enable the scan operation to allow shifting (to initialize scan cells). ? 2. After loading the scan cells, hold the scan clocks off and then apply stimulus to the primary inputs. ? 3. Measure the outputs. ? 4. Pulse the clock to capture new values into scan cells. ? 5. Enable the scan operation to unload and measure the captured values while simultaneously loading in new values via the shifting procedure (as in step 1). Before Scan After Scan TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. Design Verification, Testing and Diagnosis ?Design Verification: ? Be sure the design perform its specified behavior. ? Before silicon. ?Testing: ? Exercise the system and analyze the response to ascertain whether it behaves correctly. ? After silicon. ?Diagnosis: ? To locate the cause of misbehavior after the incorrect behavior is detected. ? After silicon. before silicon after silicon production engineering TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. ATPG Introduction for IP Team TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. What’s Structured DFT? ?Structured DFT ? Provides systematic and automatic approach to enhancing design testability. ? Goal is to increase the controllability and observability of a circuit. ? Methods: ? scan design technique
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