【正文】 TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. ATPG Introduction for IP Team TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. Agenda ? DFT Rules ? Combinational Loop ? Asynchronous Reset ? Tristate Bus Contention ? Clock Dividers ? Clock Gating ? DFT signals ? For Scan ? For debug ? Soft IP tasks and deliverables ? Scripts and Demos ? Qamp。A ?What’s it? ? DFT ? Structured DFT ? ATPG ?Terminology in Scan ? Scan cell ? Scan chain ? Scan procedure ? Scan waveform ? Scan type ? Scan fault model ? Scan Coverage TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. Agenda ? DFT Rules ? Combinational Loop ? Asynchronous Reset ? Tristate Bus Contention ? Clock Dividers ? Clock Gating ? DFT signals ? For Scan ? For debug ? Soft IP tasks and deliverables ? Scripts and Demos ? Qamp。A ?What’s it? ? DFT ? Structured DFT ? ATPG ?Terminology in Scan ? Scan cell ? Scan chain ? Scan procedure ? Scan waveform ? Scan type ? Scan fault model ? Scan Coverage TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. Design Verification, Testing and Diagnosis ?Design Verification: ? Be sure the design perform its specified behavior. ? Before silicon. ?Testing: ? Exercise the system and analyze the response to ascertain whether it behaves correctly. ? After silicon. ?Diagnosis: ? To locate the cause of misbehavior after the incorrect behavior is detected. ? After silicon. before silicon after silicon production engineering TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. What’s DFT ?DFT (Design For Test) ? Testability is a design attribute that measures how easy it is to create a program to prehensively test a manufactured design’s quality. ? Traditionally, design and test processes were kept separate, with test considered only at the end of the design cycle. ? But in contemporary design flows, test merges with design much earlier in the process, creating what is called a designfortest (DFT) process flow. ? Testable circuitry is both controllable and observable. In a testable design。 setting specific values on the primary inputs results in values on the primary outputs which indicate whether or not the internal circuitry works properly. ? To ensure maximum design testability, designers must employ special DFT techniques at specific stages in the development process. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. What’s Structured DFT? ?Structured DFT ? Provides systematic and automatic approach to enhancing design testability. ? Goal is to increase the controllability and observability of a circuit. ? Methods: ? scan design tech