【正文】 All other product or service names are the property of their respective owners. 169。A ?What’s it? ? DFT ? Structured DFT ? ATPG ?Terminology in Scan ? Scan cell ? Scan chain ? Scan procedure ? Scan waveform ? Scan type ? Scan fault model ? Scan Coverage TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. ATPG Introduction for IP Team TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. Agenda ? DFT Rules ? Combinational Loop ? Asynchronous Reset ? Tristate Bus Contention ? Clock Dividers ? Clock Gating ? DFT signals ? For Scan ? For debug ? Soft IP tasks and deliverables ? Scripts and Demos ? Qamp。 Freescale Semiconductor, Inc. 2022. Design Verification, Testing and Diagnosis ?Design Verification: ? Be sure the design perform its specified behavior. ? Before silicon. ?Testing: ? Exercise the system and analyze the response to ascertain whether it behaves correctly. ? After silicon. ?Diagnosis: ? To locate the cause of misbehavior after the incorrect behavior is detected. ? After silicon. before silicon after silicon production engineering TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. What’s ATPG ?ATPG (Automatic Test Pattern Generation) ? Test patterns (test vectors), are sets of 1s and 0s placed on primary input pins during the manufacturing test process to determine if the chip is functioning properly. ? ATE (Automatic Test Equipment) determines if the circuit is free from manufacturing defects by paring the faultfree output—which is also contained in the test pattern—with the actual output measured by the ATE. ? Goal : create a set of patterns that achieves a given test coverage. Then run it on Tester. Pass indicated no related defects exist in this chip. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. SCAN Procedure ?The operating procedure of the scan circuitry is as follows: ? 1. Enable the scan operation to allow shifting (to initialize scan cells). ? 2. After loading the scan cells, hold the scan clocks off and then apply stimulus to the primary inputs. ? 3. Measure the outputs. ? 4. Pulse the clock to capture new values into scan cells. ? 5. Enable the scan operation to unload and measure the captured values while simultaneously loading in new values via the shifting procedure (as in step 1). Before Scan After Scan TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. StuckAt Coverage Report DT Test Coverage = FU UU TI BL RE DT Fault Coverage = FU Statistics report faults faults fault class (coll.) (total) FU (full)