【正文】 nique, which modifies the internal sequential circuitry of the design. ? Builtin SelfTest (BIST) method, which inserts a device’s testing function within the device itself. ? boundary scan, which increases board testability by adding circuitry to a chip. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. What’s ATPG ?ATPG (Automatic Test Pattern Generation) ? Test patterns (test vectors), are sets of 1s and 0s placed on primary input pins during the manufacturing test process to determine if the chip is functioning properly. ? ATE (Automatic Test Equipment) determines if the circuit is free from manufacturing defects by paring the faultfree output—which is also contained in the test pattern—with the actual output measured by the ATE. ? Goal : create a set of patterns that achieves a given test coverage. Then run it on Tester. Pass indicated no related defects exist in this chip. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. Agenda ? DFT Rules ? Combinational Loop ? Asynchronous Reset ? Tristate Bus Contention ? Clock Dividers ? Clock Gating ? DFT signals ? For Scan ? For debug ? Soft IP tasks and deliverables ? Scripts and Demos ? Qamp。A ?What’s it? ? DFT ? Structured DFT ? ATPG ?Terminology in Scan ? Scan cell ? Scan chain ? Scan procedure ? Scan waveform ? Scan type ? Scan fault model ? Scan Coverage TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. SCAN Cell / SCAN Chain ?Scan Cell ? In normal operation (sc_en = 0), system data passes through the multiplexer to the D input of the flipflop, and then to the output Q. ? In scan mode (sc_en = 1), scan input data (sc_in) passes to the flipflop, and then to the scan output (sc_out). ?Scan Chain ? A set of serially linked scan cells. ? Each scan chain contains an external input pin and an external output pin that provide access to the scan cells. ? The scan chain length (N) is the number of scan cells within the scan chain. TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. SCAN Procedure ?The operating procedure of the scan circuitry is as follows: ? 1. Enable the scan operation to allow shifting (to initialize scan cells). ? 2. After loading the scan cells, hold the scan clocks off and then apply stimulus to the primary inputs. ? 3. Measure the outputs. ? 4. Pulse the clock to capture new values into scan cells. ? 5. Enable the scan operation to unload and measure the captured values while simultaneously loading in new values via the shifting procedure (as in step 1). Before Scan After Scan TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. 169。 Freescale Semiconductor, Inc. 2022. SCAN Waveform scan_clk scan_se Load shift shift shift Load / Unload shift shift shift capture capture Load / Unload capture Load / Unload capture Unload TM Freescale Semiconductor Confidential and Proprietary Information. Freescale? and the Fr