【正文】 滿 60 后向分計數(shù)器進位，分計數(shù)器滿 60 后向小時計數(shù)器進位，小時計數(shù)器按照“ 24 翻 0”規(guī)律計數(shù)。采用 1HZ 的基準信號產(chǎn)生 1S 的基準時間，秒的個位加到 10 就向秒的十位進一，秒的十位加到 6 就向分的個位進一，分的個位加到 10 就向分的十位進一，分的十位加到 6 就向時進一。數(shù)字化的鐘表給人們帶來了極大的方便。新 產(chǎn)品、新技術(shù)層出不窮，電子技術(shù)的發(fā)展更是日新月異。 系統(tǒng)由時鐘模塊、控制模塊、計時模塊、數(shù)據(jù)譯碼模塊、顯示以及組成。 本設(shè)計采用 EDA 技術(shù)，以硬件描述語言 VHDL 為系統(tǒng)邏輯描述手段設(shè)計文件，在 QUARTUSII 工具軟件環(huán)境下，采用自頂向下的設(shè)計方法，由各個基本模塊共同構(gòu)建了一個基于 FPGA 的數(shù)字鐘。 have proof functions function. The use of EDA design technology, hardwaredescription language VHDL description logic means for the system design documents, in QUAETUSII tools environment, a topdown design, by the various modules together build a FPGAbased digital clock. The main system make up of the clock module, control module, time module, data decoding module, display and broadcast module. After piling the design and simulation procedures, the programmable logic device to download verification, the system can plete the hours, minutes and seconds respectively, using keys to cleared , start and stop the digital clock. Keywords digital clock,hardware description language,VHDL,FPGA 攀枝花學院課程設(shè)計論文 數(shù)字鐘的設(shè)計 III 目 錄 摘 要 ............................................................................................................................ I ABSTRACT ..................................................................................................................... II 1 題目的意義和設(shè)計的要求 ..................................................................................... 1 題目的意義 ............................................................................................................ 1 設(shè)計的要求 ............................................................................................................ 1 2 設(shè)計的基本原理 ..................................................................................................... 2 3 設(shè)計方案 .................................................................................................................. 4 設(shè)計思路 ............................................................................................................... 4 各模塊的模塊圖和功能 .......................................................................................... 4 分頻器模塊 ..................................................................................................... 4 六進制計數(shù)器模塊 .......................................................................................... 6 十進制計數(shù)器模塊 .......................................................................................... 7 二十四進制計數(shù)器模塊 ................................................................................... 8 譯碼器模塊 ................................................................................................... 10 頂層文件模塊 ............................................................................................... 11 4 各模塊的仿真 ....................................................................................................... 14 ................................................................................................ 14 ..................................................................................... 14 ..................................................................................... 14 二十四進制計數(shù)器模塊仿真圖 .............................................................................. 14