【正文】 Predictive control algorithm is an advanced puter control algorithm, and based on parameter model without strict requirements to process model. FPGA system has strong parallel puting capability and higher speed in calculations. So inline optimization speed is raised. In the thesis, based on Xilinx integrated developing environment , using hardware description language as the programming language, IP core as the input, a improved predictivecontrol algorithm is designed and implemented using FPGA. General predictivecontrol algorithm and its improved format are introduced. The algorithm involves with many matrix calculation, so a lot of data puting and processing is needed. At the same time improvement from controller and hardware structure is obtained. FPGA array processor is used to implement predictivecontrol system. Due to the FPGA hardware implement, recurrent method for Matrix inversion in the predictivecontrol is briefly discussed. Predictivecontrol processor array structure is designed. In the design, adopting hierarchy and module method, the entire algorithm is divided into function modules, flows of function modules have been drawed. Such as overall system structure design, basic processor design, recurring matrix inversion processor array design, output prediction processor array design, control increment III calculation, parameter identification, and so on. Every functional module is simulated using software Modelsim. The simulation result is given. HDL description language is applied in the models of design. Analyzes the results of simulation and receives some useful conclusions. So inline optimization speed is raised and the size and cost is reduced, the application field is greatly expanded. Key words:Predictivecontrol algorithm。 Parallel algorithm IV 目 錄 摘 要 .................................................................................................................................. I ABSTRACT......................................................................................................................II 第 1 章 緒論 ................................................................................................................... 1 研究現(xiàn)狀概述 ..................................................................................................... 1 預(yù)測(cè)控制的發(fā)展和應(yīng)用 ..................................................................................... 3 預(yù)測(cè)控制在新應(yīng)用中面臨的問(wèn)題 ..................................................................... 4 FPGA 實(shí)現(xiàn)預(yù)測(cè)控制器的優(yōu)勢(shì) .......................................................................... 5 主要內(nèi)容 ............................................................................................................. 7 第 2 章 基礎(chǔ)知識(shí) ........................................................................................................... 8 FPGA 技術(shù) .......................................................................................................... 8 FPGA 結(jié)構(gòu) ................................................................................................ 8 FPGA 特點(diǎn) .............................................................................................. 11 SOPC 技術(shù) ........................................................................................................ 11 Nios II 嵌入式軟核處理器 .............................................................................. 13 FPGA/SOPC 開(kāi)發(fā)工具 .................................................................................... 14 FPGA/SOPC 開(kāi)發(fā)流程 .................................................................................... 16 第 3 章 廣義預(yù)測(cè)控制算法 ........................................................................................... 19 預(yù)測(cè)控制的特點(diǎn) ............................................................................................... 19 預(yù)測(cè)模型 ................................................................................................. 19 改進(jìn)的廣義預(yù)測(cè)控制算法 ............................................................................... 21 V 預(yù)測(cè)模型 ................................................................................................. 21 最小方差預(yù)報(bào)器 ..................................................................................... 22 預(yù)測(cè)輸出 ................................................................................................. 22 參考軌跡 ................................................................................................. 23 矩陣分解 ........................................................................................................... 23 遞推求逆 ........................................................................................................... 24 第 4 章 預(yù)測(cè)控制 FPGA 實(shí)現(xiàn)的基本單元介紹 .......................................................... 26 乘法加法器： ................................................................................................... 26 移位寄 存器： ................................................................................................... 27 A/D 轉(zhuǎn)換模塊： ................................................................................................ 28 D/A 轉(zhuǎn)換模塊： ................................................................................................ 30 第 5 章 預(yù)測(cè)控制器設(shè)計(jì)方案 ....................................................................................... 32 Nios II 處理器內(nèi)核 .......................................................................................... 33 JTAG UART IP 核 ............................................................................................ 35 timer IP 核 .......................................................................................................... 35 UART IP 核 .....................................................................................................